416 lines
9.3 KiB
Devicetree
416 lines
9.3 KiB
Devicetree
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a640_zap";
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};
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msm_bus: qcom,kgsl-busmon{
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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};
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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opp-553850000 {
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opp-hz = /bits/ 64 <553850000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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opp-486460000 {
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opp-hz = /bits/ 64 <486460000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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opp-379650000 {
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opp-hz = /bits/ 64 <379650000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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opp-309110000 {
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opp-hz = /bits/ 64 <309110000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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opp-215000000 {
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opp-hz = /bits/ 64 <215000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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msm_gpu: qcom,kgsl-3d0@2C00000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok"
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reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,
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<0x6900000 0x44000>, <0x780000 0x6fff>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
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"qdss_gfx", "qfprom_memory";
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interrupts = <0 300 0>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x06040000>;
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qcom,initial-pwrlevel = <5>;
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qcom,gpu-quirk-secvid-set-once;
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qcom,gpu-quirk-cx-gdsc;
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qcom,idle-timeout = <80>; //msecs
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qcom,no-nap;
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qcom,highest-bank-bit = <15>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <3>;
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qcom,snapshot-size = <0x200000>; //bytes
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
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qcom,tsens-name = "tsens_tz_sensor12";
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#cooling-cells = <2>;
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tzone-names = "gpuss-0-usr", "gpuss-1-usr";
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qcom,pm-qos-active-latency = <44>;
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clocks = <&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&clock_cpucc L3_GPU_VOTE_CLK>;
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clock-names = "rbbmtimer_clk", "mem_clk",
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"mem_iface_clk", "gmu_clk",
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"gpu_cc_ahb", "l3_vote";
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qcom,isense-clk-on-level = <1>;
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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qcom,msm-bus,name = "grp3d";
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qcom,bus-width = <32>;
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qcom,msm-bus,num-cases = <13>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>,
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<26 512 0 400000>, // 1 bus=100
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<26 512 0 600000>, // 2 bus=150
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<26 512 0 800000>, // 3 bus=200
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<26 512 0 1200000>, // 4 bus=300
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<26 512 0 1648000>, // 5 bus=412
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<26 512 0 2188000>, // 6 bus=547
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<26 512 0 2724000>, // 7 bus=681
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<26 512 0 3072000>, // 8 bus=768
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<26 512 0 4068000>, // 9 bus=1017
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<26 512 0 5184000>, // 10 bus=1296
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<26 512 0 6220000>, // 11 bus=1555
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<26 512 0 7216000>; // 12 bus=1804
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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/* GPU OPP data */
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operating-points-v2 = <&gpu_opp_table>;
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/* GPU related llc slices */
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cache-slice-names = "gpu", "gpuhtw";
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cache-slices = <&llcc 12>, <&llcc 11>;
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qcom,gpu-coresights {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-coresight";
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qcom,gpu-coresight@0 {
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reg = <0>;
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coresight-name = "coresight-gfx";
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coresight-atid = <50>;
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port {
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gfx_out_funnel_gfx: endpoint {
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remote-endpoint =
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<&funnel_gfx_in_gfx>;
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};
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};
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};
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qcom,gpu-coresight@1 {
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reg = <1>;
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coresight-name = "coresight-gfx-cx";
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coresight-atid = <51>;
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port {
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gfx_cx_out_funnel_gfx: endpoint {
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remote-endpoint =
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<&funnel_gfx_in_gfx_cx>;
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};
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};
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};
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};
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qcom,l3-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,l3-pwrlevels";
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qcom,l3-pwrlevel@0 {
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reg = <0>;
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qcom,l3-freq = <0>;
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};
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qcom,l3-pwrlevel@1 {
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reg = <1>;
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qcom,l3-freq = <864000000>;
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};
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qcom,l3-pwrlevel@2 {
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reg = <2>;
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qcom,l3-freq = <1344000000>;
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};
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};
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <553850000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <486460000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <379650000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <309110000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <215000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,cpu-to-ahb-path {
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qcom,msm-bus,name = "ahbpath";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 598 0 0>, // off
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<1 598 0 100>, // min freq
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<1 598 0 9999999>; // max freq
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x02CA0000 0x10000>;
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/* CB5(ATOS) & CB5/6/7 are protected by HYP */
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qcom,protect = <0xa0000 0xc000>;
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clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "iface_clk", "mem_clk", "mem_iface_clk";
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qcom,secure_align_mask = <0xfff>;
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qcom,retention;
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qcom,hyp_secure_alloc;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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label = "gfx3d_user";
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iommus = <&kgsl_smmu 0x0 0x401>;
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qcom,gpu-offset = <0xa8000>;
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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label = "gfx3d_secure";
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iommus = <&kgsl_smmu 0x2 0x400>;
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};
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};
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gmu: qcom,gmu@0x2C6A000 {
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label = "kgsl-gmu";
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compatible = "qcom,gpu-gmu";
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reg = <0x2c6a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "kgsl_gmu_reg",
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"kgsl_gmu_pdc_cfg",
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"kgsl_gmu_pdc_seq";
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interrupts = <0 304 0>, <0 305 0>;
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interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
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qcom,msm-bus,name = "cnoc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 10036 0 0>, // CNOC off
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<26 10036 0 100>; // CNOC on
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regulator-names = "vddcx", "vdd";
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>;
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clock-names = "gmu_clk", "cxo_clk", "axi_clk",
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"memnoc_clk", "gpu_cc_ahb";
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/* AOP mailbox for sending ACD enable and disable messages */
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mboxes = <&qmp_aop 0>;
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mbox-names = "aop";
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qcom,gmu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gmu-pwrlevels";
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/* GMU power levels must go from lowest to highest */
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qcom,gmu-pwrlevel@0 {
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reg = <0>;
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qcom,gmu-freq = <0>;
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};
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qcom,gmu-pwrlevel@1 {
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reg = <1>;
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qcom,gmu-freq = <200000000>;
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};
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};
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gmu_user: gmu_user {
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compatible = "qcom,smmu-gmu-user-cb";
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iommus = <&kgsl_smmu 0x4 0x400>;
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};
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gmu_kernel: gmu_kernel {
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compatible = "qcom,smmu-gmu-kernel-cb";
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iommus = <&kgsl_smmu 0x5 0x400>;
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};
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};
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};
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