510 lines
15 KiB
Devicetree
510 lines
15 KiB
Devicetree
/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "sm6150-lpi.dtsi"
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#include <dt-bindings/clock/qcom,audio-ext-clk.h>
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#include <dt-bindings/sound/audio-codec-port-types.h>
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&bolero {
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qcom,num-macros = <4>;
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qcom,va-without-decimation;
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slew_rate_reg1 = <0x62B6F000 0x0>;
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slew_rate_reg2 = <0x62B6F004 0x0>;
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slew_rate_val1 = <0x3333 0x0>;
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slew_rate_val2 = <0xF 0x0>;
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tx_macro: tx-macro@62ec0000 {
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compatible = "qcom,tx-macro";
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reg = <0x62ec0000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>,
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<&clock_audio_tx_2 0>;
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qcom,tx-swr-gpios = <&tx_swr_gpios>;
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qcom,tx-dmic-sample-rate = <2400000>;
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swr2: tx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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qcom,swr_master_id = <3>;
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swrm-io-base = <0x62ed0000 0x0>;
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interrupts = <0 137 0>, <0 623 0>;
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interrupt-names = "swr_master_irq", "swr_wake_irq";
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qcom,swr-wakeup-required = <1>;
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qcom,swr-num-ports = <5>;
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qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
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<2 ADC1 0x1>, <2 ADC2 0x2>,
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<3 ADC3 0x1>, <3 ADC4 0x2>,
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<4 DMIC0 0x1>, <4 DMIC1 0x2>,
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<4 DMIC2 0x4>, <4 DMIC3 0x8>,
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<5 DMIC4 0x1>, <5 DMIC5 0x2>,
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<5 DMIC6 0x4>, <5 DMIC7 0x8>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-mstr-irq-wakeup-capable = <1>;
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wcd937x_tx_slave: wcd937x-tx-slave {
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compatible = "qcom,wcd937x-slave";
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reg = <0x0 0x01170223>;
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};
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};
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};
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rx_macro: rx-macro@62ee0000 {
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compatible = "qcom,rx-macro";
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reg = <0x62ee0000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x62c25020>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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swr1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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qcom,swr_master_id = <2>;
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swrm-io-base = <0x62ef0000 0x0>;
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interrupts = <0 138 0>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <5>;
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qcom,swr-port-mapping = <1 HPH_L 0x1>,
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<1 HPH_R 0x2>, <2 CLSH 0x1>,
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<3 COMP_L 0x1>, <3 COMP_R 0x2>,
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<4 LO 0x1>, <5 DSD_L 0x1>,
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<5 DSD_R 0x2>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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wcd937x_rx_slave: wcd937x-rx-slave {
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compatible = "qcom,wcd937x-slave";
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reg = <0x0 0x01170224>;
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};
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};
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};
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wsa_macro: wsa-macro@62f00000 {
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compatible = "qcom,wsa-macro";
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reg = <0x62f00000 0x0>;
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clock-names = "wsa_core_clk", "wsa_npl_clk";
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clocks = <&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>;
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qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>;
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swr0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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qcom,swr_master_id = <1>;
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swrm-io-base = <0x62f10000 0x0>;
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interrupts = <0 136 0>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <8>;
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qcom,swr-port-mapping = <1 SPKR_L 0x1>,
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<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
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<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
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<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
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<8 SPKR_R_VI 0x3>;
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qcom,swr-num-dev = <2>;
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wsa881x_0211: wsa881x@20170211 {
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compatible = "qcom,wsa881x";
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reg = <0x0 0x20170211>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
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qcom,bolero-handle = <&bolero>;
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};
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wsa881x_0212: wsa881x@20170212 {
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compatible = "qcom,wsa881x";
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reg = <0x0 0x20170212>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
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qcom,bolero-handle = <&bolero>;
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};
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wsa881x_0213: wsa881x@21170213 {
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compatible = "qcom,wsa881x";
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reg = <0x0 0x21170213>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
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qcom,bolero-handle = <&bolero>;
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};
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wsa881x_0214: wsa881x@21170214 {
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compatible = "qcom,wsa881x";
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reg = <0x0 0x21170214>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
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qcom,bolero-handle = <&bolero>;
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};
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};
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};
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va_macro: va-macro@62f20000 {
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compatible = "qcom,va-macro";
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reg = <0x62f20000 0x0>;
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clock-names = "va_core_clk";
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clocks = <&clock_audio_va 0>;
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};
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wcd937x_codec: wcd937x-codec {
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compatible = "qcom,wcd937x-codec";
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
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<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
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<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
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<4 DSD_R 0x2 0 DSD_R>;
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qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
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<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
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<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
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<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
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<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
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<3 DMIC5 0x8 0 DMIC7>;
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qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
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qcom,rx-slave = <&wcd937x_rx_slave>;
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qcom,tx-slave = <&wcd937x_tx_slave>;
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cdc-vdd-ldo-rxtx-supply = <&L10A>;
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qcom,cdc-vdd-ldo-rxtx-voltage = <1800000 1800000>;
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qcom,cdc-vdd-ldo-rxtx-current = <25000>;
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cdc-vddpx-1-supply = <&L10A>;
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qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
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qcom,cdc-vddpx-1-current = <10000>;
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cdc-vdd-buck-supply = <&L15A>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-vdd-mic-bias-supply = <&BOB>;
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qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
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qcom,cdc-vdd-mic-bias-current = <25000>;
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qcom,cdc-micbias1-mv = <1800>;
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qcom,cdc-micbias2-mv = <1800>;
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qcom,cdc-micbias3-mv = <1800>;
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qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx",
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"cdc-vddpx-1",
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"cdc-vdd-mic-bias";
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qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
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};
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};
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&sm6150_snd {
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qcom,model = "sm6150-idp-snd-card";
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qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>;
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qcom,ext-disp-audio-rx = <1>;
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qcom,audio-routing =
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"AMIC2", "MIC BIAS2",
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"MIC BIAS2", "Analog Mic2",
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"TX DMIC0", "MIC BIAS1",
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"MIC BIAS1", "Digital Mic0",
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"TX DMIC1", "MIC BIAS1",
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"MIC BIAS1", "Digital Mic1",
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"TX DMIC2", "MIC BIAS3",
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"MIC BIAS3", "Digital Mic2",
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"TX DMIC3", "MIC BIAS3",
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"MIC BIAS3", "Digital Mic3",
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"TX_AIF1 CAP", "VA_MCLK",
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"TX_AIF2 CAP", "VA_MCLK",
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"RX AIF1 PB", "VA_MCLK",
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"RX AIF2 PB", "VA_MCLK",
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"RX AIF3 PB", "VA_MCLK",
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"RX AIF4 PB", "VA_MCLK",
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"HPHL_OUT", "VA_MCLK",
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"HPHR_OUT", "VA_MCLK",
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"AUX_OUT", "VA_MCLK",
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"IN1_HPHL", "HPHL_OUT",
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"IN2_HPHR", "HPHR_OUT",
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"IN3_AUX", "AUX_OUT",
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"TX SWR_ADC0", "ADC1_OUTPUT",
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"TX SWR_ADC2", "ADC2_OUTPUT",
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"WSA SRC0_INP", "SRC0",
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"WSA_TX DEC0_INP", "TX DEC0 MUX",
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"WSA_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC0_INP", "TX DEC0 MUX",
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"RX_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC2_INP", "TX DEC2 MUX",
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"RX_TX DEC3_INP", "TX DEC3 MUX",
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"SpkrLeft IN", "WSA_SPK1 OUT",
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"SpkrRight IN", "WSA_SPK2 OUT",
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"WSA_SPK1 OUT", "VA_MCLK",
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"WSA_SPK2 OUT", "VA_MCLK";
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qcom,msm-mbhc-hphl-swh = <1>;
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qcom,msm-mbhc-gnd-swh = <1>;
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qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
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qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
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asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
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asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
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"msm-ext-disp-audio-codec-rx";
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qcom,wsa-max-devs = <2>;
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qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
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<&wsa881x_0213>, <&wsa881x_0214>;
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qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
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"SpkrLeft", "SpkrRight";
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qcom,codec-max-aux-devs = <1>;
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qcom,codec-aux-devs = <&wcd937x_codec>;
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qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
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<&lpi_tlmm>, <&bolero>;
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};
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&soc {
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cdc_dmic01_gpios: cdc_dmic01_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
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pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
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qcom,lpi-gpios;
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};
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cdc_dmic23_gpios: cdc_dmic23_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
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pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
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qcom,lpi-gpios;
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};
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wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
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pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
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};
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rx_swr_gpios: rx_swr_clk_data_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>;
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pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>;
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qcom,lpi-gpios;
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};
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tx_swr_gpios: tx_swr_clk_data_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
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&tx_swr_data2_active>;
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pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
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&tx_swr_data2_sleep>;
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qcom,lpi-gpios;
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};
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wsa_spkr_en1: wsa_spkr_en1_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&spkr_1_sd_n_active>;
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pinctrl-1 = <&spkr_1_sd_n_sleep>;
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};
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wsa_spkr_en2: wsa_spkr_en2_pinctrl {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&spkr_2_sd_n_active>;
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pinctrl-1 = <&spkr_2_sd_n_sleep>;
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};
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wcd9xxx_intc: wcd9xxx-irq {
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status = "disabled";
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compatible = "qcom,wcd9xxx-irq";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&tlmm>;
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qcom,gpio-connect = <&tlmm 122 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&wcd_intr_default>;
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};
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wcd934x_rst_gpio: msm_cdc_pinctrl@29 {
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status = "disabled";
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&lpi_wcd934x_reset_active>;
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pinctrl-1 = <&lpi_wcd934x_reset_sleep>;
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qcom,lpi-gpios;
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};
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wcd937x_rst_gpio: msm_cdc_pinctrl@24 {
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compatible = "qcom,msm-cdc-pinctrl";
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pinctrl-names = "aud_active", "aud_sleep";
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pinctrl-0 = <&lpi_wcd937x_reset_active>;
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pinctrl-1 = <&lpi_wcd937x_reset_sleep>;
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qcom,lpi-gpios;
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};
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tavil_glink: qcom,wcd-dsp-glink {
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status = "disabled";
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compatible = "qcom,wcd-dsp-glink";
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qcom,wdsp-channels = "g_glink_ctrl",
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"g_glink_persistent_data_nild",
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"g_glink_persistent_data_ild",
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"g_glink_audio_data";
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};
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tavil_wdsp: wcd-dsp-mgr@2 {
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status = "disabled";
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compatible = "qcom,wcd-dsp-mgr";
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qcom,wdsp-components = <&wcd934x_cdc 0>,
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<&tavil_spi_0 1>,
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<&glink_spi_xprt_wdsp 2>;
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qcom,img-filename = "cpe_9340";
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};
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clock_audio_wsa_1: wsa_core_clk {
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compatible = "qcom,audio-ref-clk";
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qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
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qcom,codec-lpass-ext-clk-freq = <19200000>;
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qcom,codec-lpass-clk-id = <0x309>;
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#clock-cells = <1>;
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};
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clock_audio_wsa_2: wsa_npl_clk {
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compatible = "qcom,audio-ref-clk";
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qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
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qcom,codec-lpass-ext-clk-freq = <19200000>;
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qcom,codec-lpass-clk-id = <0x30A>;
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#clock-cells = <1>;
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};
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clock_audio_va: va_core_clk {
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compatible = "qcom,audio-ref-clk";
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qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_1>;
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qcom,codec-lpass-ext-clk-freq = <19200000>;
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qcom,codec-lpass-clk-id = <0x30B>;
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#clock-cells = <1>;
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};
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clock_audio_rx_1: rx_core_clk {
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compatible = "qcom,audio-ref-clk";
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qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
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qcom,codec-lpass-ext-clk-freq = <22579200>;
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qcom,codec-lpass-clk-id = <0x30E>;
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#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_2: rx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
|
|
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
|
qcom,codec-lpass-clk-id = <0x30F>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_tx_1: tx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30C>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_tx_2: tx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30D>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio: audio_ext_clk {
|
|
status = "disabled";
|
|
qcom,codec-ext-clk-src = <0>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&wcd934x_mclk_default>;
|
|
pinctrl-1 = <&wcd934x_mclk_default>;
|
|
qcom,use-pinctrl = <1>;
|
|
qcom,audio-ref-clk-gpio = <&pm6150_gpios 8 0>;
|
|
clock-names = "osr_clk";
|
|
clocks = <&pm6150_clkdiv>;
|
|
qcom,node_has_rpm_clock;
|
|
pmic-clock-names = "pm6150_div_clk1";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dbu1: dbu1 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "dbu1";
|
|
startup-delay-us = <0>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
&slim_aud {
|
|
wcd934x_cdc: tavil_codec {
|
|
status = "disabled";
|
|
compatible = "qcom,tavil-slim-pgd";
|
|
elemental-addr = [00 01 50 02 17 02];
|
|
|
|
interrupt-parent = <&wcd9xxx_intc>;
|
|
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
|
|
17 18 19 20 21 22 23 24 25 26 27 28 29
|
|
30 31>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd934x_rst_gpio>;
|
|
|
|
clock-names = "wcd_clk";
|
|
clocks = <&clock_audio 0>;
|
|
|
|
cdc-vdd-buck-supply = <&dbu1>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <594000>;
|
|
|
|
cdc-buck-sido-supply = <&dbu1>;
|
|
qcom,cdc-buck-sido-voltage = <1800000 1800000>;
|
|
qcom,cdc-buck-sido-current = <500000>;
|
|
|
|
cdc-vdd-tx-h-supply = <&dbu1>;
|
|
qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-tx-h-current = <25000>;
|
|
|
|
cdc-vdd-rx-h-supply = <&dbu1>;
|
|
qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rx-h-current = <25000>;
|
|
|
|
cdc-vddpx-1-supply = <&dbu1>;
|
|
qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
|
|
qcom,cdc-vddpx-1-current = <10000>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
|
qcom,cdc-vdd-mic-bias-current = <30400 1000001>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-buck",
|
|
"cdc-buck-sido",
|
|
"cdc-vdd-tx-h",
|
|
"cdc-vdd-rx-h",
|
|
"cdc-vddpx-1";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
|
|
|
|
qcom,cdc-micbias1-mv = <1800>;
|
|
qcom,cdc-micbias2-mv = <1800>;
|
|
qcom,cdc-micbias3-mv = <1800>;
|
|
qcom,cdc-micbias4-mv = <1800>;
|
|
|
|
qcom,cdc-mclk-clk-rate = <9600000>;
|
|
qcom,cdc-slim-ifd = "tavil-slim-ifd";
|
|
qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02];
|
|
qcom,cdc-dmic-sample-rate = <4800000>;
|
|
qcom,cdc-mad-dmic-rate = <600000>;
|
|
|
|
qcom,wdsp-cmpnt-dev-name = "tavil_codec";
|
|
qcom,vreg-micb-supply = <&BOB>;
|
|
|
|
tavil_spi_0: wcd_spi {
|
|
compatible = "qcom,wcd-spi-v2";
|
|
qcom,master-bus-num = <0>;
|
|
qcom,chip-select = <0>;
|
|
qcom,max-frequency = <24000000>;
|
|
qcom,mem-base-addr = <0x100000>;
|
|
};
|
|
};
|
|
};
|