286 lines
6.7 KiB
Devicetree
286 lines
6.7 KiB
Devicetree
/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,gcc-sdxprairie.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x1c00000 0x4000>,
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<0x1c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"iatu", "conf";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc 0 140 0
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0 0 0 1 &intc 0 141 0
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0 0 0 2 &intc 0 142 0
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0 0 0 3 &intc 0 143 0
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0 0 0 4 &intc 0 144 0>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x1010 0x00 0x0
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0x101c 0x31 0x0
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0x1020 0x01 0x0
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0x1024 0xce 0x0
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0x1028 0x0b 0x0
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0x1030 0x97 0x0
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0x1034 0x0c 0x0
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0x1044 0x18 0x0
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0x1048 0x90 0x0
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0x1058 0x0f 0x0
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0x1074 0x06 0x0
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0x1078 0x06 0x0
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0x107c 0x16 0x0
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0x1080 0x16 0x0
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0x1084 0x36 0x0
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0x1088 0x36 0x0
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0x1094 0x08 0x0
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0x10a4 0x46 0x0
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0x10a8 0x04 0x0
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0x10ac 0x04 0x0
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0x10b0 0x0d 0x0
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0x10b4 0x0a 0x0
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0x10b8 0x1a 0x0
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0x10bc 0xc3 0x0
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0x10c4 0xd0 0x0
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0x10d4 0x05 0x0
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0x10d8 0x55 0x0
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0x10dc 0x55 0x0
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0x10e0 0x05 0x0
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0x110c 0x02 0x0
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0x1154 0x34 0x0
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0x1158 0x12 0x0
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0x115c 0x00 0x0
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0x1168 0x05 0x0
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0x116c 0x04 0x0
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0x119c 0x88 0x0
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0x11a0 0x03 0x0
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0x11ac 0xca 0x0
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0x11b0 0x1e 0x0
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0x11b4 0xd8 0x0
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0x11b8 0x20 0x0
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0x11bc 0x22 0x0
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0x106c 0x0a 0x0
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0x1070 0x10 0x0
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0x11a4 0x05 0x0
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0x11a8 0x0f 0x0
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0x008c 0x06 0x0
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0x00e0 0x01 0x0
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0x00c4 0x01 0x0
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0x0258 0x16 0x0
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0x0378 0x83 0x0
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0x0360 0xe2 0x0
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0x0364 0x04 0x0
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0x0368 0x30 0x0
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0x0370 0xff 0x0
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0x03cc 0x42 0x0
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0x03d0 0x0d 0x0
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0x03d4 0x77 0x0
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0x03d8 0x2d 0x0
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0x03dc 0x39 0x0
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0x03e0 0x9f 0x0
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0x03e4 0x0f 0x0
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0x03e8 0x63 0x0
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0x03ec 0xbf 0x0
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0x03f0 0x79 0x0
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0x03f4 0x4f 0x0
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0x03f8 0x0f 0x0
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0x03fc 0xd5 0x0
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0x02ac 0x7f 0x0
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0x0310 0x55 0x0
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0x0334 0x0c 0x0
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0x0338 0x00 0x0
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0x0350 0x0f 0x0
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0x088c 0x06 0x0
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0x08e0 0x01 0x0
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0x08c4 0x01 0x0
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0x0a58 0x16 0x0
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0x0b78 0x83 0x0
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0x0b60 0xe2 0x0
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0x0b64 0x04 0x0
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0x0b68 0x30 0x0
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0x0b70 0xff 0x0
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0x0bcc 0x42 0x0
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0x0bd0 0x0d 0x0
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0x0bd4 0x77 0x0
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0x0bd8 0x2d 0x0
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0x0bdc 0x39 0x0
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0x0be0 0x9f 0x0
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0x0be4 0x0f 0x0
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0x0be8 0x63 0x0
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0x0bec 0xbf 0x0
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0x0bf0 0x79 0x0
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0x0bf4 0x4f 0x0
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0x0bf8 0x0f 0x0
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0x0bfc 0xd5 0x0
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0x0aac 0x7f 0x0
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0x0b10 0x55 0x0
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0x0b34 0x0c 0x0
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0x0b38 0x00 0x0
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0x0b50 0x0f 0x0
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0x161c 0xc1 0x0
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0x1690 0x00 0x0
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0x13e4 0x03 0x0
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0x1708 0x03 0x0
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0x16a0 0x16 0x0
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0x13e0 0x16 0x0
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0x13d8 0x01 0x0
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0x16fc 0x01 0x0
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0x13dc 0x00 0x0
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0x1700 0x00 0x0
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0x1828 0x50 0x0
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0x1c28 0x50 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_default
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&pcie0_wake_default>;
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perst-gpio = <&tlmm 57 0>;
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wake-gpio = <&tlmm 53 0>;
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gdsc-vdd-supply = <&gdsc_pcie>;
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vreg-1.8-supply = <&pmxprairie_l1>;
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vreg-0.9-supply = <&pmxprairie_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1.8-voltage-level = <1200000 1200000 15000>;
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qcom,vreg-0.9-voltage-level = <872000 872000 47900>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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msi-parent = <&pcie0_msi>;
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qcom,target-link-speed = <0x3>;
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qcom,no-l0s-supported;
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qcom,l1-2-th-scale = <2>; /* 1us */
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qcom,l1-2-th-value = <70>;
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qcom,ep-latency = <10>;
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qcom,slv-addr-space-size = <0x40000000>;
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qcom,pcie-phy-ver = <0x1096>;
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qcom,use-19p2mhz-aux-clk;
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qcom,phy-status-offset = <0x1214>;
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qcom,phy-status-bit = <7>;
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qcom,phy-power-down-offset = <0x1240>;
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qcom,boot-option = <0x1>;
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linux,pci-domain = <0>;
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qcom,smmu-sid-base = <0x0200>;
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iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
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<0x100 &apps_smmu 0x0201 0x1>,
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<0x200 &apps_smmu 0x0202 0x1>,
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<0x300 &apps_smmu 0x0203 0x1>,
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<0x400 &apps_smmu 0x0204 0x1>,
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<0x208 &apps_smmu 0x0205 0x1>,
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<0x210 &apps_smmu 0x0206 0x1>;
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qcom,msm-bus,name = "pcie0";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>,
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<45 512 500 800>;
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clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_AUX_CLK>,
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<&clock_gcc GCC_PCIE_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
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<&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_PCIE_SLEEP_CLK>,
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<&clock_gcc GCC_PCIE_RCHNG_PHY_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_0_sleep_clk", "pcie_phy_refgen_clk";
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max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>;
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resets = <&clock_gcc GCC_PCIE_BCR>,
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<&clock_gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:010c";
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/* BDF 1.0.0 */
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pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 {
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reg = <0 0 0 0 0>;
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pci-ids = "12d8:b304";
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errata = <0>;
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/* BDF 2.1.0 */
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pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 {
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reg = <0x800 0 0 0 0>;
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pci-ids = "12d8:b304";
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errata = <1>;
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};
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/* BDF 2.2.0 */
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pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 {
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reg = <0x1000 0 0 0 0>;
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pci-ids = "12d8:b304";
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errata = <2>;
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};
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};
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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};
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