285 lines
6.9 KiB
Plaintext
285 lines
6.9 KiB
Plaintext
* Qualcomm Technologies, Inc. MSM Camera ICP
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The MSM camera ICP devices are implemented multiple device nodes.
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The root icp device node has properties defined to hint the driver
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about the number of A5,IPE and BPS nodes available during the
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probe sequence. Each node has multiple properties defined
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for interrupts, clocks and regulators.
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=======================
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Required Node Structure
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=======================
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ICP root interface node takes care of the handling account for number
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of A5, IPE and BPS devices present on the hardware.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,cam-icp".
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- compat-hw-name
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,a5" or "qcom,ipe0" or "qcom,ipe1" or "qcom,bps".
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- num-a5
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Usage: required
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Value type: <u32>
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Definition: Number of supported A5 processors.
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- num-ipe
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Usage: required
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Value type: <u32>
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Definition: Number of supported IPE HW blocks.
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- num-bps
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Usage: required
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Value type: <u32>
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Definition: Number of supported BPS HW blocks.
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- icp_pc_en
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Usage: optional
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Value type: boolean
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Definition: Specifies ICP power collapse enablement
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- ipe_bps_pc_en
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Usage: optional
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Value type: boolean
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Definition: Specifies IPE/BPS power collapse enablement
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Example:
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qcom,cam-icp {
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compatible = "qcom,cam-icp";
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compat-hw-name = "qcom,a5", "qcom,ipe0", "qcom,ipe1", "qcom,bps";
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num-a5 = <1>;
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num-ipe = <2>;
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num-bps = <1>;
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icp_pc_en;
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ipe_bps_pc_en;
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status = "ok";
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};
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=======================
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Required Node Structure
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=======================
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A5/IPE/BPS Node's provides interface for Image Control Processor driver
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about the A5 register map, interrupt map, clocks, regulators
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and name of firmware image.
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- cell-index
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Usage: required
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Value type: <u32>
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Definition: Node instance number.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Should be "qcom,cam-a5" or "qcom,cam-ipe" or "qcom,cam-bps".
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- reg-names
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Usage: optional
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Value type: <string>
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Definition: Name of the register resources.
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- reg
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Usage: optional
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Value type: <u32>
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Definition: Register values.
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- reg-cam-base
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Usage: optional
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Value type: <u32>
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Definition: Register values.
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- interrupt-names
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Usage: optional
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Value type: <string>
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Definition: Name of the interrupt.
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- interrupts
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Usage: optional
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Value type: <u32>
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Definition: Interrupt associated with CDM HW.
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- regulator-names
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Usage: required
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Value type: <string>
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Definition: Name of the regulator resources for CDM HW.
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- camss-supply
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Usage: required
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Value type: <phandle>
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Definition: Regulator reference corresponding to the names listed
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in "regulator-names".
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- clock-names
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Usage: required
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Value type: <string>
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Definition: List of clock names required for CDM HW.
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- src-clock-name
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Usage: required
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Value type: <string>
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Definition: Source clock name.
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- clock-control-debugfs
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Usage: optional
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Value type: <string>
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Definition: Enable/Disable clk rate control.
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- clocks
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Usage: required
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Value type: <phandle>
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Definition: List of clocks used for CDM HW.
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- clock-cntl-level
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Usage: required
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Value type: <string>
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Definition: List of strings corresponds clock-rates levels.
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Supported strings: lowsvs, svs, svs_l1, nominal, turbo.
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- clock-rates
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Usage: required
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Value type: <u32>
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Definition: List of clocks rates.
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- fw_name
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Usage: optional
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Value type: <string>
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Definition: Name of firmware image.
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- ubwc-cfg
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Usage: required
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Value type: <u32>
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Definition: UBWC configuration.
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- qcom,cam-cx-ipeak:
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Usage: optional
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Value type: <phandle bit>
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phandle - phandle of CX Ipeak device node
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bit - Every bit corresponds to a client of CX Ipeak
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Definition: CX Ipeak is a mitigation scheme which throttles camera frequency
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if all the clients are running at their respective threshold
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frequencies to limit CX peak current.
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driver in the relevant register.
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Examples:
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a5: qcom,a5@ac00000 {
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cell-index = <0>;
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compatible = "qcom,cam-a5";
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reg = <0xac00000 0x6000>,
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<0xac10000 0x8000>,
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<0xac18000 0x3000>;
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reg-names = "a5_qgic", "a5_sierra", "a5_csr";
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interrupts = <0 463 0>;
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interrupt-names = "a5";
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regulator-names = "camss-vdd";
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camss-vdd-supply = <&titan_top_gdsc>;
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clock-names = "gcc_cam_ahb_clk",
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"gcc_cam_axi_clk",
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"soc_ahb_clk",
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"cpas_ahb_clk",
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"camnoc_axi_clk",
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"icp_apb_clk",
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"icp_atb_clk",
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"icp_clk",
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"icp_clk_src",
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"icp_cti_clk",
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"icp_ts_clk";
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clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
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<&clock_gcc GCC_CAMERA_AXI_CLK>,
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<&clock_camcc CAM_CC_SOC_AHB_CLK>,
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<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
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<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&clock_camcc CAM_CC_ICP_APB_CLK>,
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<&clock_camcc CAM_CC_ICP_ATB_CLK>,
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<&clock_camcc CAM_CC_ICP_CLK>,
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<&clock_camcc CAM_CC_ICP_CLK_SRC>,
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<&clock_camcc CAM_CC_ICP_CTI_CLK>,
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<&clock_camcc CAM_CC_ICP_TS_CLK>;
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clock-rates = <0 0 0 80000000 0 0 0 0 600000000 0 0>;
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clock-cntl-level = "turbo";
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fw_name = "CAMERA_ICP.elf";
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ubwc-cfg = <0x7F 0x1FF>;
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};
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qcom,ipe0 {
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cell-index = <0>;
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compatible = "qcom,cam-ipe";
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regulator-names = "ipe0-vdd";
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ipe0-vdd-supply = <&ipe_0_gdsc>;
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clock-names = "ipe_0_ahb_clk",
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"ipe_0_areg_clk",
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"ipe_0_axi_clk",
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"ipe_0_clk",
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"ipe_0_clk_src";
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src-clock-name = "ipe_0_clk_src";
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clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
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<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
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<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
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<&clock_camcc CAM_CC_IPE_0_CLK>,
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<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;
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clock-rates = <0 0 0 0 240000000>,
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<0 0 0 0 404000000>,
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<0 0 0 0 480000000>,
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<0 0 0 0 538000000>,
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<0 0 0 0 600000000>;
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clock-cntl-level = "lowsvs", "svs",
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"svs_l1", "nominal", "turbo";
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};
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qcom,ipe1 {
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cell-index = <1>;
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compatible = "qcom,cam-ipe";
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regulator-names = "ipe1-vdd";
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ipe1-vdd-supply = <&ipe_1_gdsc>;
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clock-names = "ipe_1_ahb_clk",
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"ipe_1_areg_clk",
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"ipe_1_axi_clk",
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"ipe_1_clk",
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"ipe_1_clk_src";
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src-clock-name = "ipe_1_clk_src";
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clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,
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<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
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<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,
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<&clock_camcc CAM_CC_IPE_1_CLK>,
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<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;
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clock-rates = <0 0 0 0 240000000>,
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<0 0 0 0 404000000>,
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<0 0 0 0 480000000>,
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<0 0 0 0 538000000>,
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<0 0 0 0 600000000>;
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clock-cntl-level = "lowsvs", "svs",
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"svs_l1", "nominal", "turbo";
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qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>;
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};
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bps: qcom,bps {
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cell-index = <0>;
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compatible = "qcom,cam-bps";
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regulator-names = "bps-vdd";
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bps-vdd-supply = <&bps_gdsc>;
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clock-names = "bps_ahb_clk",
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"bps_areg_clk",
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"bps_axi_clk",
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"bps_clk",
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"bps_clk_src";
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src-clock-name = "bps_clk_src";
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clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,
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<&clock_camcc CAM_CC_BPS_AREG_CLK>,
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<&clock_camcc CAM_CC_BPS_AXI_CLK>,
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<&clock_camcc CAM_CC_BPS_CLK>,
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<&clock_camcc CAM_CC_BPS_CLK_SRC>;
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clock-rates = <0 0 0 0 200000000>,
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<0 0 0 0 404000000>,
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<0 0 0 0 480000000>,
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<0 0 0 0 600000000>,
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<0 0 0 0 600000000>;
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clock-cntl-level = "lowsvs", "svs",
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"svs_l1", "nominal", "turbo";
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};
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