41 lines
1.7 KiB
Plaintext
41 lines
1.7 KiB
Plaintext
* GIC EDAC node:
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GIC EDAC node is defined to describe on-chip error or fault detection and correction
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for GIC RAM. GICT(GIC trace and debug) register map describes the syndrome information
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and GICT support is available from GIC-600 onwards.
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GIC EDAC reports all Single Bit Error and Double Bit Error found in GIC RAM.
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Current GIC ECC implementation is interrupt based. GIC scrub feature helps
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to avoid potential errors accumulation of particular error location by a write-back
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of all valid RAM entries periodically.
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GICT identifies software programming errors, correctable and uncorrectable
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errors of Shared Peripheral Interrupt(SPI) RAM, Software Generated Interrupt(SGI) RAM,
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Private Peripheral Interrupt(PPI) RAM, Locality-Specific Peripheral Interrupt(LPI) RAM
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and Interrupt Translation Service (ITS) RAM.
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For every error record following information available -
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ERRXSTATUS - Error Record Status Register
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ERRXMISC0 - Error Record Miscellaneous Register 0
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ERRXMISC1 - Error Record Miscellaneous Register 1
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ERRXADDR - Error Record Address Resister
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The following section describes the DT node binding for gic-erp.
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Required properties:
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- compatible : "arm,gic-600-erp".
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- reg-names : GIC Trace, GIC Distributor, GIC Redistributor bases
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- interrupt-config : SPI interrupt numbers of Fault and Error interrupts
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to configure GICT_ERRORQCR0, GICT_ERRORQCR1 registers respectively.
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- interrupts : Interrupts for Fault and Error IRQs
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gict: gict@17a20000 {
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compatible = "arm,gic-600-erp";
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reg = <0x17a20000 0x10000>; /* GICT */
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reg-names = "gict-base";
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interrupt-config = <46, 17>;
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interrupt-names = "gict-fault", "gict-err";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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