594 lines
16 KiB
C
594 lines
16 KiB
C
/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/clk/msm-clk-provider.h>
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#include <linux/clk/msm-clk.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <dt-bindings/clock/msm-clocks-8974.h>
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#include "mdss-pll.h"
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#include "mdss-edp-pll.h"
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#define EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG (0x0)
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#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG (0x0004)
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#define EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG (0x000C)
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#define EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020)
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#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG (0x0024)
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#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG (0x0028)
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#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0 (0x0038)
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#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1 (0x003C)
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#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2 (0x0040)
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#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3 (0x0044)
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#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4 (0x0048)
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#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0 (0x004C)
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#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1 (0x0050)
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#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2 (0x0054)
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#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3 (0x0058)
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#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0 (0x006C)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2 (0x0074)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6 (0x0084)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7 (0x0088)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8 (0x008C)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9 (0x0090)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10 (0x0094)
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#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11 (0x0098)
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#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0 (0x005C)
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#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1 (0x0060)
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#define EDP_PLL_POLL_DELAY_US 50
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#define EDP_PLL_POLL_TIMEOUT_US 500
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static const struct clk_ops edp_mainlink_clk_src_ops;
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static struct clk_div_ops fixed_5div_ops; /* null ops */
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static const struct clk_ops edp_pixel_clk_ops;
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static inline struct edp_pll_vco_clk *to_edp_vco_clk(struct clk *clk)
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{
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return container_of(clk, struct edp_pll_vco_clk, c);
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}
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int edp_div_prepare(struct clk *c)
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{
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struct div_clk *div = to_div_clk(c);
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/* Restore the divider's value */
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return div->ops->set_div(div, div->data.div);
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}
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static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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struct mdss_pll_resources *edp_pll_res = vco->priv;
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int rc;
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pr_debug("vco_rate=%d\n", (int)vco_rate);
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rc = mdss_pll_resource_enable(edp_pll_res, true);
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if (rc) {
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pr_err("failed to enable edp pll res rc=%d\n", rc);
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rc = -EINVAL;
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}
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if (vco_rate == 810000000) {
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x18);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x69);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0xff);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x2f);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x2a);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x3);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
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} else if (vco_rate == 1350000000) {
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x01);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x62);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x28);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x46);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x5);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
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} else {
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pr_err("rate=%d is NOT supported\n", (int)vco_rate);
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vco_rate = 0;
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rc = -EINVAL;
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}
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(100);
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mdss_pll_resource_enable(edp_pll_res, false);
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vco->rate = vco_rate;
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return rc;
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}
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static int edp_pll_ready_poll(struct mdss_pll_resources *edp_pll_res)
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{
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int cnt;
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u32 status;
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cnt = 100;
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while (cnt--) {
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udelay(100);
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status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
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status &= 0x01;
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if (status)
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break;
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}
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pr_debug("cnt=%d status=%d\n", cnt, (int)status);
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if (status)
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return 1;
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return 0;
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}
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static int edp_vco_enable(struct clk *c)
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{
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int i, ready;
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int rc;
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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struct mdss_pll_resources *edp_pll_res = vco->priv;
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rc = mdss_pll_resource_enable(edp_pll_res, true);
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if (rc) {
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pr_err("edp pll resources not available\n");
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return rc;
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}
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for (i = 0; i < 3; i++) {
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ready = edp_pll_ready_poll(edp_pll_res);
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if (ready)
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break;
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
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udelay(100);
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MDSS_PLL_REG_W(edp_pll_res->pll_base,
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EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(100);
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}
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if (ready) {
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pr_debug("EDP PLL lock success\n");
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edp_pll_res->pll_on = true;
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rc = 0;
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} else {
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pr_err("EDP PLL failed to lock\n");
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mdss_pll_resource_enable(edp_pll_res, false);
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rc = -EINVAL;
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}
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return rc;
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}
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static void edp_vco_disable(struct clk *c)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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struct mdss_pll_resources *edp_pll_res = vco->priv;
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if (!edp_pll_res) {
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pr_err("Invalid input parameter\n");
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return;
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}
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if (!edp_pll_res->pll_on &&
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mdss_pll_resource_enable(edp_pll_res, true)) {
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pr_err("edp pll resources not available\n");
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return;
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}
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MDSS_PLL_REG_W(edp_pll_res->pll_base, 0x20, 0x00);
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edp_pll_res->handoff_resources = false;
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edp_pll_res->pll_on = false;
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mdss_pll_resource_enable(edp_pll_res, false);
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pr_debug("EDP PLL Disabled\n");
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}
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static unsigned long edp_vco_get_rate(struct clk *c)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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struct mdss_pll_resources *edp_pll_res = vco->priv;
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u32 pll_status, div2;
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int rc;
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if (is_gdsc_disabled(edp_pll_res))
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return 0;
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rc = mdss_pll_resource_enable(edp_pll_res, true);
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if (rc) {
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pr_err("edp pll resources not available\n");
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return rc;
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}
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if (vco->rate == 0) {
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pll_status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
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if (pll_status & 0x01) {
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div2 = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0x24);
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if (div2 & 0x01)
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vco->rate = 1350000000;
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else
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vco->rate = 810000000;
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}
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}
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mdss_pll_resource_enable(edp_pll_res, false);
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pr_debug("rate=%d\n", (int)vco->rate);
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return vco->rate;
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}
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static long edp_vco_round_rate(struct clk *c, unsigned long rate)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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unsigned long rrate = -ENOENT;
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unsigned long *lp;
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lp = vco->rate_list;
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while (*lp) {
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rrate = *lp;
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if (rate <= rrate)
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break;
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lp++;
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}
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pr_debug("rrate=%d\n", (int)rrate);
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return rrate;
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}
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static int edp_vco_prepare(struct clk *c)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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pr_debug("rate=%d\n", (int)vco->rate);
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return edp_vco_set_rate(c, vco->rate);
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}
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static void edp_vco_unprepare(struct clk *c)
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{
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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pr_debug("rate=%d\n", (int)vco->rate);
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edp_vco_disable(c);
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}
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static int edp_pll_lock_status(struct mdss_pll_resources *edp_pll_res)
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{
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u32 status;
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int pll_locked = 0;
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int rc;
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rc = mdss_pll_resource_enable(edp_pll_res, true);
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if (rc) {
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pr_err("edp pll resources not available\n");
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return rc;
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}
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/* poll for PLL ready status */
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if (readl_poll_timeout_atomic((edp_pll_res->pll_base + 0xc0),
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status, ((status & BIT(0)) == 1),
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EDP_PLL_POLL_DELAY_US,
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EDP_PLL_POLL_TIMEOUT_US)) {
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pr_debug("EDP PLL status=%x failed to Lock\n", status);
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pll_locked = 0;
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} else {
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pll_locked = 1;
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}
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mdss_pll_resource_enable(edp_pll_res, false);
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return pll_locked;
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}
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static enum handoff edp_vco_handoff(struct clk *c)
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{
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enum handoff ret = HANDOFF_DISABLED_CLK;
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struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
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struct mdss_pll_resources *edp_pll_res = vco->priv;
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|
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if (is_gdsc_disabled(edp_pll_res))
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return HANDOFF_DISABLED_CLK;
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if (mdss_pll_resource_enable(edp_pll_res, true)) {
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pr_err("edp pll resources not available\n");
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return ret;
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}
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|
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edp_pll_res->handoff_resources = true;
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|
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if (edp_pll_lock_status(edp_pll_res)) {
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c->rate = edp_vco_get_rate(c);
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edp_pll_res->pll_on = true;
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ret = HANDOFF_ENABLED_CLK;
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} else {
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edp_pll_res->handoff_resources = false;
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mdss_pll_resource_enable(edp_pll_res, false);
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}
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|
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pr_debug("done, ret=%d\n", ret);
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return ret;
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}
|
|
|
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static unsigned long edp_vco_rate_list[] = {
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810000000, 1350000000, 0};
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|
|
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struct const clk_ops edp_vco_clk_ops = {
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.enable = edp_vco_enable,
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.set_rate = edp_vco_set_rate,
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.get_rate = edp_vco_get_rate,
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.round_rate = edp_vco_round_rate,
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.prepare = edp_vco_prepare,
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.unprepare = edp_vco_unprepare,
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.handoff = edp_vco_handoff,
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|
};
|
|
|
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struct edp_pll_vco_clk edp_vco_clk = {
|
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.ref_clk_rate = 19200000,
|
|
.rate = 0,
|
|
.rate_list = edp_vco_rate_list,
|
|
.c = {
|
|
.dbg_name = "edp_vco_clk",
|
|
.ops = &edp_vco_clk_ops,
|
|
CLK_INIT(edp_vco_clk.c),
|
|
},
|
|
};
|
|
|
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static unsigned long edp_mainlink_get_rate(struct clk *c)
|
|
{
|
|
struct div_clk *mclk = to_div_clk(c);
|
|
struct clk *pclk;
|
|
unsigned long rate = 0;
|
|
|
|
pclk = clk_get_parent(c);
|
|
|
|
if (pclk && pclk->ops->get_rate) {
|
|
rate = pclk->ops->get_rate(pclk);
|
|
rate /= mclk->data.div;
|
|
}
|
|
|
|
pr_debug("rate=%d div=%d\n", (int)rate, mclk->data.div);
|
|
|
|
return rate;
|
|
}
|
|
|
|
|
|
struct div_clk edp_mainlink_clk_src = {
|
|
.ops = &fixed_5div_ops,
|
|
.data = {
|
|
.div = 5,
|
|
.min_div = 5,
|
|
.max_div = 5,
|
|
},
|
|
.c = {
|
|
.parent = &edp_vco_clk.c,
|
|
.dbg_name = "edp_mainlink_clk_src",
|
|
.ops = &edp_mainlink_clk_src_ops,
|
|
.flags = CLKFLAG_NO_RATE_CACHE,
|
|
CLK_INIT(edp_mainlink_clk_src.c),
|
|
}
|
|
};
|
|
|
|
/*
|
|
* this rate is from pll to clock controller
|
|
* output from pll to CC has two possibilities
|
|
* 1: if mainlink rate is 270M, then 675M
|
|
* 2: if mainlink rate is 162M, then 810M
|
|
*/
|
|
static int edp_pixel_set_div(struct div_clk *clk, int div)
|
|
{
|
|
int rc;
|
|
struct mdss_pll_resources *edp_pll_res = clk->priv;
|
|
|
|
rc = mdss_pll_resource_enable(edp_pll_res, true);
|
|
if (rc) {
|
|
pr_err("edp pll resources not available\n");
|
|
return rc;
|
|
}
|
|
|
|
pr_debug("div=%d\n", div);
|
|
MDSS_PLL_REG_W(edp_pll_res->pll_base,
|
|
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, (div - 1));
|
|
mdss_pll_resource_enable(edp_pll_res, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int edp_pixel_get_div(struct div_clk *clk)
|
|
{
|
|
int div = 0;
|
|
int rc;
|
|
struct mdss_pll_resources *edp_pll_res = clk->priv;
|
|
|
|
if (is_gdsc_disabled(edp_pll_res))
|
|
return 0;
|
|
|
|
rc = mdss_pll_resource_enable(edp_pll_res, true);
|
|
if (rc) {
|
|
pr_err("edp pll resources not available\n");
|
|
return rc;
|
|
}
|
|
|
|
div = MDSS_PLL_REG_R(edp_pll_res->pll_base,
|
|
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG);
|
|
mdss_pll_resource_enable(edp_pll_res, false);
|
|
div &= 0x01;
|
|
pr_debug("div=%d\n", div);
|
|
return div + 1;
|
|
}
|
|
|
|
static struct clk_div_ops edp_pixel_ops = {
|
|
.set_div = edp_pixel_set_div,
|
|
.get_div = edp_pixel_get_div,
|
|
};
|
|
|
|
struct div_clk edp_pixel_clk_src = {
|
|
.data = {
|
|
.max_div = 2,
|
|
.min_div = 1,
|
|
},
|
|
.ops = &edp_pixel_ops,
|
|
.c = {
|
|
.parent = &edp_vco_clk.c,
|
|
.dbg_name = "edp_pixel_clk_src",
|
|
.ops = &edp_pixel_clk_ops,
|
|
.flags = CLKFLAG_NO_RATE_CACHE,
|
|
CLK_INIT(edp_pixel_clk_src.c),
|
|
},
|
|
};
|
|
|
|
static struct clk_lookup mdss_edp_pllcc_8974[] = {
|
|
CLK_LOOKUP("edp_pixel_src", edp_pixel_clk_src.c,
|
|
"fd8c0000.qcom,mmsscc-mdss"),
|
|
CLK_LOOKUP("edp_mainlink_src", edp_mainlink_clk_src.c,
|
|
"fd8c0000.qcom,mmsscc-mdss"),
|
|
};
|
|
|
|
int edp_pll_clock_register(struct platform_device *pdev,
|
|
struct mdss_pll_resources *pll_res)
|
|
{
|
|
int rc = -ENOTSUPP;
|
|
|
|
if (!pll_res || !pll_res->pll_base) {
|
|
pr_err("Invalid input parameters\n");
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
/* Set client data to div and vco clocks */
|
|
edp_pixel_clk_src.priv = pll_res;
|
|
edp_mainlink_clk_src.priv = pll_res;
|
|
edp_vco_clk.priv = pll_res;
|
|
|
|
/* Set clock operation for mainlink and pixel clock */
|
|
edp_mainlink_clk_src_ops = clk_ops_div;
|
|
edp_mainlink_clk_src_ops.get_parent = clk_get_parent;
|
|
edp_mainlink_clk_src_ops.get_rate = edp_mainlink_get_rate;
|
|
|
|
edp_pixel_clk_ops = clk_ops_slave_div;
|
|
edp_pixel_clk_ops.prepare = edp_div_prepare;
|
|
|
|
rc = of_msm_clock_register(pdev->dev.of_node, mdss_edp_pllcc_8974,
|
|
ARRAY_SIZE(mdss_edp_pllcc_8974));
|
|
if (rc) {
|
|
pr_err("Clock register failed rc=%d\n", rc);
|
|
rc = -EPROBE_DEFER;
|
|
}
|
|
|
|
return rc;
|
|
}
|