1684 lines
30 KiB
Devicetree
1684 lines
30 KiB
Devicetree
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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tlmm: pinctrl@3400000 {
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compatible = "qcom,sdmmagpie-pinctrl";
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reg = <0x03400000 0xdc2000>, <0x17c000f0 0x60>;
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reg-names = "pinctrl", "spi_cfg";
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interrupts = <0 208 0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ufs_dev_reset_assert: ufs_dev_reset_assert {
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config {
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pins = "ufs_reset";
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bias-pull-down; /* default: pull down */
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/*
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* UFS_RESET driver strengths are having
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* different values/steps compared to typical
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* GPIO drive strengths.
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*
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* Following table clarifies:
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*
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* HDRV value | UFS_RESET | Typical GPIO
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* (dec) | (mA) | (mA)
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* 0 | 0.8 | 2
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* 1 | 1.55 | 4
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* 2 | 2.35 | 6
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* 3 | 3.1 | 8
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* 4 | 3.9 | 10
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* 5 | 4.65 | 12
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* 6 | 5.4 | 14
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* 7 | 6.15 | 16
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*
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* POR value for UFS_RESET HDRV is 3 which means
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* 3.1mA and we want to use that. Hence just
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* specify 8mA to "drive-strength" binding and
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* that should result into writing 3 to HDRV
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* field.
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*/
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drive-strength = <8>; /* default: 3.1 mA */
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output-low; /* active low reset */
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};
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};
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ufs_dev_reset_deassert: ufs_dev_reset_deassert {
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config {
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pins = "ufs_reset";
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bias-pull-down; /* default: pull down */
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/*
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* default: 3.1 mA
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* check comments under ufs_dev_reset_assert
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*/
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drive-strength = <8>;
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output-high; /* active low reset */
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};
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};
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/* QUPv3 South SE mappings */
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/* SE 0 pin mappings */
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_active: qupv3_se0_i2c_active {
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mux {
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pins = "gpio49", "gpio50";
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function = "qup00";
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};
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config {
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pins = "gpio49", "gpio50";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio49", "gpio50";
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function = "gpio";
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};
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config {
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pins = "gpio49", "gpio50";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se0_spi_pins: qupv3_se0_spi_pins {
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qupv3_se0_spi_active: qupv3_se0_spi_active {
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mux {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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function = "qup00";
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};
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config {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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function = "gpio";
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};
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config {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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/* SE 1 pin mappings */
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_active: qupv3_se1_i2c_active {
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mux {
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pins = "gpio0", "gpio1";
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function = "qup01";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_active: qupv3_se1_spi_active {
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mux {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3";
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function = "qup01";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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/* SE 2 pin mappings */
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qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
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qupv3_se2_i2c_active: qupv3_se2_i2c_active {
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mux {
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pins = "gpio34", "gpio35";
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function = "qup02";
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};
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config {
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pins = "gpio34", "gpio35";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
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mux {
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pins = "gpio34", "gpio35";
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function = "gpio";
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};
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config {
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pins = "gpio34", "gpio35";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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nfc {
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nfc_int_active: nfc_int_active {
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/* active state */
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mux {
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/* GPIO 37 NFC Read Interrupt */
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pins = "gpio37";
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function = "gpio";
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};
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config {
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pins = "gpio37";
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drive-strength = <2>; /* 2 MA */
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bias-pull-up;
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};
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};
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nfc_int_suspend: nfc_int_suspend {
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/* sleep state */
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mux {
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/* GPIO 37 NFC Read Interrupt */
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pins = "gpio37";
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function = "gpio";
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};
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config {
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pins = "gpio37";
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drive-strength = <2>; /* 2 MA */
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bias-pull-up;
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};
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};
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nfc_enable_active: nfc_enable_active {
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/* active state */
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mux {
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/* 12: Enable 36: Firmware */
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pins = "gpio12", "gpio36";
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function = "gpio";
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};
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config {
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pins = "gpio12", "gpio36";
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drive-strength = <2>; /* 2 MA */
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bias-pull-up;
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};
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};
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nfc_enable_suspend: nfc_enable_suspend {
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/* sleep state */
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mux {
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/* 12: Enable 36: Firmware */
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pins = "gpio12", "gpio36";
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function = "gpio";
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};
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config {
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pins = "gpio12", "gpio36";
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drive-strength = <2>; /* 2 MA */
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bias-disable;
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};
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};
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nfc_clk_req_active: nfc_clk_req_active {
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/* active state */
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mux {
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/* GPIO 31: NFC CLOCK REQUEST */
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pins = "gpio31";
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function = "gpio";
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};
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config {
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pins = "gpio31";
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drive-strength = <2>; /* 2 MA */
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bias-pull-up;
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};
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};
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nfc_clk_req_suspend: nfc_clk_req_suspend {
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/* sleep state */
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mux {
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/* GPIO 31: NFC CLOCK REQUEST */
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pins = "gpio31";
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function = "gpio";
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};
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config {
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pins = "gpio31";
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drive-strength = <2>; /* 2 MA */
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bias-disable;
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};
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};
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};
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/* SE 3 pin mappings */
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qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
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qupv3_se3_i2c_active: qupv3_se3_i2c_active {
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mux {
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pins = "gpio38", "gpio39";
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function = "qup03";
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};
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config {
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pins = "gpio38", "gpio39";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
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mux {
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pins = "gpio38", "gpio39";
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function = "gpio";
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};
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config {
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pins = "gpio38", "gpio39";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
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qupv3_se3_ctsrx: qupv3_se3_ctsrx {
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mux {
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pins = "gpio38", "gpio41";
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function = "qup03";
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};
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config {
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pins = "gpio38", "gpio41";
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drive-strength = <2>;
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bias-no-pull;
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};
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};
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qupv3_se3_rts: qupv3_se3_rts {
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mux {
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pins = "gpio39";
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function = "qup03";
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};
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config {
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pins = "gpio39";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_tx: qupv3_se3_tx {
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mux {
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pins = "gpio40";
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function = "qup03";
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};
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config {
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pins = "gpio40";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se3_spi_pins: qupv3_se3_spi_pins {
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qupv3_se3_spi_active: qupv3_se3_spi_active {
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mux {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41";
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function = "qup03";
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};
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config {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
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mux {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41";
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function = "gpio";
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};
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config {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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fpc_reset_int {
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fpc_reset_low: reset_low {
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mux {
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pins = "gpio91";
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function = "gpio";
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};
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config {
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pins = "gpio91";
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drive-strength = <2>;
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bias-disable;
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output-low;
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};
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};
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fpc_reset_high: reset_high {
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mux {
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pins = "gpio91";
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function = "gpio";
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};
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config {
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pins = "gpio91";
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drive-strength = <2>;
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bias-disable;
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output-high;
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};
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};
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fpc_int_low: int_low {
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mux {
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pins = "gpio90";
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function = "gpio";
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};
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config {
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pins = "gpio90";
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drive-strength = <2>;
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bias-pull-down;
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input-enable;
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};
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};
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};
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/* SE 4 pin mappings */
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qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
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qupv3_se4_i2c_active: qupv3_se4_i2c_active {
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mux {
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pins = "gpio53", "gpio54";
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function = "qup04";
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};
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config {
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pins = "gpio53", "gpio54";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
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mux {
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pins = "gpio53", "gpio54";
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function = "gpio";
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};
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config {
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pins = "gpio53", "gpio54";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se4_4uart_pins: qupv3_se4_4uart_pins {
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qupv3_se4_ctsrx: qupv3_se4_ctsrx {
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mux {
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pins = "gpio53", "gpio56";
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function = "qup04";
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};
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config {
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pins = "gpio53", "gpio56";
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drive-strength = <2>;
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bias-no-pull;
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};
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};
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qupv3_se4_rts: qupv3_se4_rts {
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mux {
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pins = "gpio54";
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function = "qup04";
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};
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config {
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pins = "gpio54";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se4_tx: qupv3_se4_tx {
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mux {
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pins = "gpio55";
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function = "qup04";
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};
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config {
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pins = "gpio55";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se4_spi_pins: qupv3_se4_spi_pins {
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qupv3_se4_spi_active: qupv3_se4_spi_active {
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mux {
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pins = "gpio53", "gpio54", "gpio55",
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"gpio56";
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function = "qup04";
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};
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config {
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pins = "gpio53", "gpio54", "gpio55",
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"gpio56";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
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mux {
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pins = "gpio53", "gpio54", "gpio55",
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"gpio56";
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function = "gpio";
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};
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config {
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pins = "gpio53", "gpio54", "gpio55",
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"gpio56";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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/* QUPv3 North instances */
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/* SE 6 pin mappings */
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qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
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qupv3_se6_i2c_active: qupv3_se6_i2c_active {
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mux {
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pins = "gpio59", "gpio60";
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function = "qup10";
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};
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config {
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pins = "gpio59", "gpio60";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
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mux {
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pins = "gpio59", "gpio60";
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function = "gpio";
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};
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config {
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pins = "gpio59", "gpio60";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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qupv3_se6_spi_pins: qupv3_se6_spi_pins {
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qupv3_se6_spi_active: qupv3_se6_spi_active {
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mux {
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pins = "gpio59", "gpio60", "gpio61",
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"gpio62";
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function = "qup10";
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};
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config {
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pins = "gpio59", "gpio60", "gpio61",
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"gpio62";
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drive-strength = <6>;
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bias-disable;
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};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
|
|
mux {
|
|
pins = "gpio59", "gpio60", "gpio61",
|
|
"gpio62";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59", "gpio60", "gpio61",
|
|
"gpio62";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SE 7 pin mappings */
|
|
qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
|
|
qupv3_se7_i2c_active: qupv3_se7_i2c_active {
|
|
mux {
|
|
pins = "gpio6", "gpio7";
|
|
function = "qup11";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
|
|
mux {
|
|
pins = "gpio6", "gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_pins: qupv3_se7_spi_pins {
|
|
qupv3_se7_spi_active: qupv3_se7_spi_active {
|
|
mux {
|
|
pins = "gpio6", "gpio7", "gpio8",
|
|
"gpio9";
|
|
function = "qup11";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7", "gpio8",
|
|
"gpio9";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
|
|
mux {
|
|
pins = "gpio6", "gpio7", "gpio8",
|
|
"gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7", "gpio8",
|
|
"gpio9";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SE 8 pin mappings */
|
|
qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
|
|
qupv3_se8_i2c_active: qupv3_se8_i2c_active {
|
|
mux {
|
|
pins = "gpio42", "gpio43";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio43";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
|
|
mux {
|
|
pins = "gpio42", "gpio43";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio43";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_pins: qupv3_se8_2uart_pins {
|
|
qupv3_se8_2uart_active: qupv3_se8_2uart_active {
|
|
mux {
|
|
pins = "gpio44", "gpio45";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44", "gpio45";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep {
|
|
mux {
|
|
pins = "gpio44", "gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44", "gpio45";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_pins: qupv3_se8_spi_pins {
|
|
qupv3_se8_spi_active: qupv3_se8_spi_active {
|
|
mux {
|
|
pins = "gpio42", "gpio43", "gpio44",
|
|
"gpio45";
|
|
function = "qup12";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio43", "gpio44",
|
|
"gpio45";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
|
|
mux {
|
|
pins = "gpio42", "gpio43", "gpio44",
|
|
"gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio43", "gpio44",
|
|
"gpio45";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SE 9 pin mappings */
|
|
qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
|
|
qupv3_se9_i2c_active: qupv3_se9_i2c_active {
|
|
mux {
|
|
pins = "gpio46", "gpio47";
|
|
function = "qup13";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio46", "gpio47";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
|
|
mux {
|
|
pins = "gpio46", "gpio47";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SE 10 pin mappings */
|
|
qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
|
|
qupv3_se10_i2c_active: qupv3_se10_i2c_active {
|
|
mux {
|
|
pins = "gpio110", "gpio111";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio111";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
|
|
mux {
|
|
pins = "gpio110", "gpio111";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio111";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_4uart_pins: qupv3_se10_4uart_pins {
|
|
qupv3_se10_ctsrx: qupv3_se10_ctsrx {
|
|
mux {
|
|
pins = "gpio110", "gpio113";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio113";
|
|
drive-strength = <2>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_rts: qupv3_se10_rts {
|
|
mux {
|
|
pins = "gpio111";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio111";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_tx: qupv3_se10_tx {
|
|
mux {
|
|
pins = "gpio112";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_pins: qupv3_se10_spi_pins {
|
|
qupv3_se10_spi_active: qupv3_se10_spi_active {
|
|
mux {
|
|
pins = "gpio110", "gpio111", "gpio112",
|
|
"gpio113";
|
|
function = "qup14";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio111", "gpio112",
|
|
"gpio113";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
|
|
mux {
|
|
pins = "gpio110", "gpio111", "gpio112",
|
|
"gpio113";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio111", "gpio112",
|
|
"gpio113";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SE 11 pin mappings */
|
|
qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
|
|
qupv3_se11_i2c_active: qupv3_se11_i2c_active {
|
|
mux {
|
|
pins = "gpio101", "gpio102";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101", "gpio102";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
|
|
mux {
|
|
pins = "gpio101", "gpio102";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101", "gpio102";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_4uart_pins: qupv3_se11_4uart_pins {
|
|
qupv3_se11_ctsrx: qupv3_se11_ctsrx {
|
|
mux {
|
|
pins = "gpio101", "gpio92";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101", "gpio92";
|
|
drive-strength = <2>;
|
|
bias-no-pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_rts: qupv3_se11_rts {
|
|
mux {
|
|
pins = "gpio102";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio102";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_tx: qupv3_se11_tx {
|
|
mux {
|
|
pins = "gpio103";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio103";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_pins: qupv3_se11_spi_pins {
|
|
qupv3_se11_spi_active: qupv3_se11_spi_active {
|
|
mux {
|
|
pins = "gpio101", "gpio102", "gpio103",
|
|
"gpio92";
|
|
function = "qup15";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101", "gpio102", "gpio103",
|
|
"gpio92";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
|
|
mux {
|
|
pins = "gpio101", "gpio102", "gpio103",
|
|
"gpio92";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101", "gpio102", "gpio103",
|
|
"gpio92";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_sde_te {
|
|
sde_te_active: sde_te_active {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_te_suspend: sde_te_suspend {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
|
|
sde_te1_active: sde_te1_active {
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_te1_suspend: sde_te1_suspend {
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_dp_aux_active: sde_dp_aux_active {
|
|
mux {
|
|
pins = "gpio42", "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio33";
|
|
bias-disable = <0>; /* no pull */
|
|
drive-strength = <8>;
|
|
};
|
|
};
|
|
|
|
sde_dp_aux_suspend: sde_dp_aux_suspend {
|
|
mux {
|
|
pins = "gpio42", "gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42", "gpio33";
|
|
bias-pull-down;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
|
|
mux {
|
|
pins = "gpio104";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
bias-disable;
|
|
drive-strength = <16>;
|
|
};
|
|
};
|
|
|
|
sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
|
|
mux {
|
|
pins = "gpio104";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
bias-pull-down;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
wsa_swr_clk_pin {
|
|
wsa_swr_clk_sleep: wsa_swr_clk_sleep {
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "wsa_clk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <2>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
wsa_swr_clk_active: wsa_swr_clk_active {
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "wsa_clk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <2>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa_swr_data_pin {
|
|
wsa_swr_data_sleep: wsa_swr_data_sleep {
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "wsa_data";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <4>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
|
|
wsa_swr_data_active: wsa_swr_data_active {
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "wsa_data";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <4>;
|
|
bias-bus-hold;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* WSA speaker reset pins */
|
|
spkr_1_sd_n {
|
|
spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_1_sd_n_active: spkr_1_sd_n_active {
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <16>; /* 16 mA */
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
spkr_2_sd_n {
|
|
spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_2_sd_n_active: spkr_2_sd_n_active {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <16>; /* 16 mA */
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
wcd9xxx_intr {
|
|
wcd_intr_default: wcd_intr_default{
|
|
mux {
|
|
pins = "gpio58";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio58";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* pull down */
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
fsa_usbc_ana_en_n@42 {
|
|
fsa_usbc_ana_en: fsa_usbc_ana_en {
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
cci0_active: cci0_active {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio17","gpio18"; // Only 2
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17","gpio18";
|
|
bias-pull-up; /* PULL UP*/
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci0_suspend: cci0_suspend {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio17","gpio18";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17","gpio18";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci1_active: cci1_active {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio19","gpio20";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19","gpio20";
|
|
bias-pull-up; /* PULL UP*/
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci1_suspend: cci1_suspend {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio19","gpio20";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19","gpio20";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci2_active: cci2_active {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio27","gpio28";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27","gpio28";
|
|
bias-pull-up; /* PULL UP*/
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci2_suspend: cci2_suspend {
|
|
mux {
|
|
/* CLK, DATA */
|
|
pins = "gpio27","gpio28";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27","gpio28";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
|
|
/* MCLK0 */
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
|
|
/* MCLK0 */
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_active: cam_sensor_mclk1_active {
|
|
/* MCLK1 */
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
|
|
/* MCLK1 */
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_active: cam_sensor_mclk2_active {
|
|
/* MCLK2 */
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
|
|
/* MCLK2 */
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_active: cam_sensor_mclk3_active {
|
|
/* MCLK3 */
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
|
|
/* MCLK3 */
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
/* SDC pin type */
|
|
sdc1_clk_on: sdc1_clk_on {
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <16>; /* 16 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_clk_off: sdc1_clk_off {
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_on: sdc1_cmd_on {
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_off: sdc1_cmd_off {
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
num-grp-pins = <1>;
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_data_on: sdc1_data_on {
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_data_off: sdc1_data_off {
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_on: sdc1_rclk_on {
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down; /* pull down */
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_off: sdc1_rclk_off {
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down; /* pull down */
|
|
};
|
|
};
|
|
|
|
sdc2_clk_on: sdc2_clk_on {
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <16>; /* 16 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_clk_off: sdc2_clk_off {
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_on: sdc2_cmd_on {
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_off: sdc2_cmd_off {
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_data_on: sdc2_data_on {
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_data_off: sdc2_data_off {
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cd_on: cd_on {
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_cd_off: cd_off {
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pmx_ts_active {
|
|
ts_active: ts_active {
|
|
mux {
|
|
pins = "gpio8", "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_suspend {
|
|
ts_int_suspend: ts_int_suspend {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_suspend {
|
|
ts_reset_suspend: ts_reset_suspend {
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_release {
|
|
ts_release: ts_release {
|
|
mux {
|
|
pins = "gpio9", "gpio8";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9", "gpio8";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pm6150_gpios {
|
|
wcd934x_mclk {
|
|
wcd934x_mclk_default: wcd934x_mclk_default{
|
|
pins = "gpio8";
|
|
function = "func1";
|
|
qcom,drive-strength = <2>;
|
|
power-source = <0>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pm6150l_gpios {
|
|
disp_pins {
|
|
disp_pins_default: disp_pins_default{
|
|
pins = "gpio9";
|
|
function = "func1";
|
|
qcom,drive-strength = <2>;
|
|
power-source = <1>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
};
|