145 lines
3.8 KiB
Devicetree
145 lines
3.8 KiB
Devicetree
/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,gcc-qcs405.h>
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&soc {
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pcie0: qcom,pcie@7780000 {
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compatible = "qcom,pci-msm";
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cell-index = <0>;
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reg = <0x7780000 0x2000>,
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<0x7786000 0x1000>,
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<0x10000000 0xf1d>,
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<0x10000f20 0xa8>,
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<0x10100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi",
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"conf";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x10200000 0x10200000 0x0 0x100000>,
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<0x02000000 0x0 0x10300000 0x10300000 0x0 0xd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4 5 6 7 8 9 10>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc 0 269 0
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0 0 0 1 &intc 0 68 0
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0 0 0 2 &intc 0 224 0
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0 0 0 3 &intc 0 267 0
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0 0 0 4 &intc 0 268 0
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0 0 0 5 &intc 0 270 0
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0 0 0 6 &intc 0 271 0
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0 0 0 7 &intc 0 272 0
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0 0 0 8 &intc 0 273 0
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0 0 0 9 &intc 0 274 0
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0 0 0 10 &intc 0 275 0 >;
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interrupt-names = "int_pls_pme", "int_a", "int_b", "int_c",
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"int_d", "int_pme_legacy", "int_pls_err",
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"int_aer_legacy", "int_pls_link_up",
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"int_pls_link_down", "int_bridge_flush_n";
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qcom,phy-sequence = <0x00a0 0x0 0x0
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0x00a4 0x01 0x3E8
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0x0044 0x01 0x0
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0x0088 0x78 0x0
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0x008c 0x78 0x0
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0x0074 0x24 0x0
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0x0078 0x1a 0x0
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0x007c 0x18 0x0
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0x0084 0x04 0x0
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0x0094 0x00 0x0
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0x0080 0x00 0x0
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0x0044 0x00 0x0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_perst_default>;
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perst-gpio = <&tlmm 43 0>;
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vreg-1.8-supply = <&pms405_l5>;
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vreg-0.9-supply = <&pms405_l3>;
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qcom,vreg-0.9-voltage-level = <1160000 976000 24000>;
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msi-parent = <&pcie0_msi>;
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qcom,ep-latency = <10>;
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qcom,phy-status-offset = <0x3c>;
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qcom,phy-status-bit = <0>;
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qcom,phy-power-down-offset = <0x98>;
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qcom,core-preset = <0x77777777>;
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qcom,boot-option = <0x0>;
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qcom,keep-powerdown-phy;
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qcom,no-l0s-supported;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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linux,pci-domain = <0>;
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qcom,msm-bus,name = "pcie0";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_PCIE
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MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_PCIE
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MSM_BUS_SLAVE_EBI_CH0 500 800>;
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clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
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<&clock_cmn_blk_pll CMN_BLK_PLL>,
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<&clock_gcc GCC_PCIE_0_AUX_CLK>,
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<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&clock_rpmcc RPM_SMD_LN_BB_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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max-clock-frequency-hz = <250000000>, <0>, <1200000>,
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<0>, <0>, <0>, <0>;
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clock-output-names = "pcie_0_pipe_clk";
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resets = <&clock_gcc GCC_PCIEPHY_0_PHY_BCR>,
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<&clock_gcc GCC_PCIE_0_BCR>,
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<&clock_gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_phy_reset",
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"pcie_0_core_reset",
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"pcie_phy_reset";
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pcie_rc0: pcie_rc0 {
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#address-cells = <5>;
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#size-cells = <0>;
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reg = <0 0 0 0 0>;
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pci-ids = "17cb:1000";
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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};
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