33 lines
865 B
Plaintext
33 lines
865 B
Plaintext
* Kryo EDAC node
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Kryo EDAC node is defined to describe on-chip error detection and correction
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for the Kryo core.
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Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers:
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ERRXSTATUS - Error Record Primary Status Register
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ERRXMISC0 - Error Record Miscellaneous Register
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Current implementation of Kryo ECC mechanism is based on interrupts.
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The following section describes the DT node binding for kryo_cpu_erp.
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Required properties:
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- compatible : Shall be "arm,arm64-kryo-cpu-erp".
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- interrupts : Interrupt-specifier for L1/L2, L3/SCU error IRQ(s)
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- interrupt-names : Descriptive names of the interrupts
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Example:
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kryo-erp {
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compatible = "arm,arm64-kryo-cpu-erp";
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interrupts = <1 6 4>,
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<1 7 4>,
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<0 34 4>,
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<0 35 4>;
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interrupt-names = "l1-l2-faultirq",
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"l1-l2-errirq",
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"l3-scu-errirq",
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"l3-scu-faultirq";
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};
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