264 lines
12 KiB
Plaintext
264 lines
12 KiB
Plaintext
Qualcomm Technologies, Inc.
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sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.
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DP Controller: Required properties:
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- compatible: Should be "qcom,dp-display".
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- reg: Base address and length of DP hardware's memory mapped regions.
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- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
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"dp_phy" - DP PHY memory region.
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"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
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"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
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"dp_mmss_cc" - Display Clock Control memory region.
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"qfprom_physical" - QFPROM Phys memory region.
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"dp_pll" - USB3 DP combo PLL memory region.
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"usb3_dp_com" - USB3 DP PHY combo memory region.
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"hdcp_physical" - DP HDCP memory region.
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- cell-index: Specifies the controller instance.
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- clocks: Clocks required for Display Port operation.
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- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
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"core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",
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"core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",
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"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent", "bond_pixel_parent".
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Only under multiple DPs pixel clock bonding mode, i.e. triple DPs bonding, bond_pixel_parent
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is used, replacing the pixel_parent for single DP mode.
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- gdsc-supply: phandle to gdsc regulator node.
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- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
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- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
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- interrupt-parent phandle to the interrupt parent device node.
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- interrupts: The interrupt signal from the DSI block.
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- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
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- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
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- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
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- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port.
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- qcom,mst-enable: MST feature enable control node.
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- qcom,dsc-feature-enable: DSC feature enable control node.
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- qcom,fec-feature-enable: FEC feature enable control node.
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- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port.
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- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block.
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- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection.
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- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation.
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- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch.
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- qcom,dp-gpio-aux-switch:» Gpio DP AUX switch chipset support.
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- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"
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can be "core", "ctrl", and "phy". Within the same type,
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there can be more than one instance of this binding,
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in which case the entry would be appended with the
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supply entry index.
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e.g. qcom,ctrl-supply-entry@0
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-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
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-- qcom,supply-min-voltage: minimum voltage level (uV)
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-- qcom,supply-max-voltage: maximum voltage level (uV)
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-- qcom,supply-enable-load: load drawn (uA) from enabled supply
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-- qcom,supply-disable-load: load drawn (uA) from disabled supply
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-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
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-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
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-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
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-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
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msm_ext_disp is a device which manages the interaction between external
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display interfaces, e.g. Display Port, and the audio subsystem.
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Optional properties:
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- qcom,intf-index: u32 integer array to specify the intf instances
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- qcom,phy-index: u32 integer to specify the phy instance
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- qcom,ext-disp: phandle for msm-ext-display module
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- compatible: Must be "qcom,msm-ext-disp"
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- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node
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- qcom,phy-version: Phy version
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- qcom,phy-mode: Phy mode from the following list. If not specified, the default PHY mode is decided by the PHY driver,
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which is "dp" for DP/USB combo PHY, "edp" for eDP/DP combo PHY
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"dp" - DP PHY mode
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"minidp" - MiniDP PHY mode
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"edp" - eDP PHY mode
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"edp-highswing" - eDP PHY mode, high swing/pre-emphasis
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- qcom,pn-swap-lane-map: P/N swap configuration of each lane
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- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node
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Refer to pinctrl-bindings.txt
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- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin
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controller. These pin configurations are installed in the pinctrl
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device node. Refer to pinctrl-bindings.txt
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- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port.
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- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one
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- qcom,dp-aux-bridge: phandle for dp aux bridge module, for 3rd party dp bridge only.
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- qcom,dp-aux-bridge-sim: phandle for dp aux bridge module, for internal mst debug simulation only.
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- qcom,dp-force-bond-mode: Ignore tile information from EDID and force DP to work in bond mode.
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- qcom,dp-force-connect-mode: Boolean to specify if dp is in always-connected mode, only set
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when qcom,dp-aux-bridge is defined. Once set, dp will always
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report connected state to user. When HPD is high, mode from sink
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will be reported. When HPD is low, mode from dp-aux-bridge
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simulator will be reported.
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- qcom,bond-dual-ctrl: u32 array to specify the cell-index of the two DP controllers that support bond mode.
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The first controller in the array is the bond master. Driver will switch to bond mode
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if both DP controllers are connected to the same dual DP input monitor.
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e.g. <1, 0> will bond DP0 and DP1, and DP1 is the master, and DP0 is the salve.
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- qcom,bond-tri-ctrl: u32 array to specify the cell-index of the three DP controllers that support bond mode.
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The first controller in the array is the bond master. Driver will switch to bond mode
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if all three DP controllers are connected to the same triple DP input monitor.
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e.g. <2, 0, 1> will bond DP0, DP1 and DP2 together, and DP2 is the master, DP0/DP1 are the slaves.
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[Optional child nodes]: These nodes are for devices which are
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dependent on msm_ext_disp. If msm_ext_disp is disabled then
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these devices will be disabled as well. Ex. Audio Codec device.
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- ext_disp_audio_codec: Node for Audio Codec.
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- compatible : "qcom,msm-ext-disp-audio-codec-rx";
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Example:
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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};
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sde_dp: qcom,dp_display@0{
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cell-index = <0>;
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compatible = "qcom,dp-display";
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gdsc-supply = <&mdss_core_gdsc>;
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vdda-1p2-supply = <&pm8998_l26>;
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vdda-0p9-supply = <&pm8998_l1>;
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reg = <0xae90000 0xa84>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0xaf02000 0x1a0>,
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<0x780000 0x621c>,
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<0x88ea030 0x10>,
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<0x88e8000 0x621c>,
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<0x0aee1000 0x034>;
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reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_mmss_cc", "qfprom_physical", "dp_pll",
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"usb3_dp_com", "hdcp_physical";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
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"core_usb_ref_clk", "core_usb_cfg_ahb_clk",
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"core_usb_pipe_clk", "ctrl_link_clk",
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"ctrl_link_iface_clk", "ctrl_crypto_clk",
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"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";
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qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
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qcom,ext-disp = <&ext_disp>;
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qcom,phy-version = <0x420>;
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,aux-cfg0-settings = [1c 00];
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qcom,aux-cfg1-settings = [20 13 23 1d];
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qcom,aux-cfg2-settings = [24 00];
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qcom,aux-cfg3-settings = [28 00];
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qcom,aux-cfg4-settings = [2c 0a];
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qcom,aux-cfg5-settings = [30 26];
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qcom,aux-cfg6-settings = [34 0a];
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qcom,aux-cfg7-settings = [38 03];
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qcom,aux-cfg8-settings = [3c bb];
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qcom,aux-cfg9-settings = [40 03];
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qcom,max-pclk-frequency-khz = <593470>;
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qcom,mst-enable;
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qcom,dsc-feature-enable;
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qcom,fec-feature-enable;
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qcom,max-dp-dsc-blks = <2>;
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qcom,max-dp-dsc-input-width-pixs = <2048>;
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pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
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pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
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pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
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qcom,aux-en-gpio = <&tlmm 43 0>;
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qcom,aux-sel-gpio = <&tlmm 51 0>;
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qcom,usbplug-cc-gpio = <&tlmm 38 0>;
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <21800>;
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qcom,supply-disable-load = <4>;
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};
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};
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <880000>;
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qcom,supply-enable-load = <36000>;
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qcom,supply-disable-load = <32>;
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};
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};
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};
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};
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