70 lines
2.4 KiB
Plaintext
70 lines
2.4 KiB
Plaintext
Qualcomm Technologies, Inc. QCS405 CPU clock driver
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---------------------------------------------------
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It is the clock controller driver which provides higher frequency
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clocks and allows CPU frequency scaling on qcs405 based platforms.
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Required properties:
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- compatible: Shall contain following:
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"qcom,cpu-qcs405"
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"qcom,cpu-sdxprairie"
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- clocks: Phandle to the clock device.
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- clock-names: Names of the used clocks. Shall contain following:
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"xo_ao", "gpll0_ao"
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- reg: Shall contain base register offset and size.
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- reg-names: Names of the bases for the above registers. Shall contain following:
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"apcs_cmd", "apcs_pll"
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- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
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- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
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- cpu-vdd-supply: The regulator powering the APSS RCG.
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- qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
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Format: <freq uV>
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This represents the max frequency possible for each possible
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power configuration for a CPU that's binned as speed bin X,
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speed bin revision Z. Version can be between [0-3].
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- #clock-cells: Shall contain 1.
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Optional properties:
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- reg-names: "efuse"
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- qcom,cpucc-init-rate: Initial rate which needs to be set from cpu driver.
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Example:
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clock_cpu: qcom,clock-cpu@0b011050 {
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compatible = "qcom,cpu-qcs405";
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clocks = <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&clock_gcc GPLL0_AO_OUT_MAIN>;
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clock-names = "xo_ao", "gpll0_ao" ;
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qcom,cpucc-init-rate = <960000000>;
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reg = <0x0b011050 0x8>,
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<0xb016000 0x34>;
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reg-names = "apcs_cmd" , "apcs_pll";
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cpu-vdd-supply = <&apc_vreg_corner>;
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vdd_dig_ao-supply = <&pmd9655_s1_level_ao>;
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vdd_hf_pll-supply = <&pms405_l5_ao>;
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qcom,speed0-bin-v0 =
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< 0 0>,
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< 960000000 1>,
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< 1113600000 2>,
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< 1267200000 3>,
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< 1382400000 4>;
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#clock-cells = <1>;
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};
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clock_cpu: qcom,clock-cpu@17808100 {
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compatible = "qcom,cpu-sdxprairie";
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clocks = <&clock_rpmh RPMH_CXO_CLK>>;
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clock-names = "&clock_rpmh RPMH_CXO_CLK";
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reg = <0x17810008 0x8>,
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<0x17808100 0x44>;
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reg-names = "apcs_cmd" , "apcs_pll";
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vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
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cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
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qcom,speed0-bin-v0 =
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< 0 RPMH_REGULATOR_LEVEL_OFF>,
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< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
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< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
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< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
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< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;
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#clock-cells = <1>;
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};
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