/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include &soc { /* Primary USB port related controller */ usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x0a600000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x140 0x0>; qcom,smmu-s1-bypass; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_prim_gdsc>; clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, <&clock_rpmh RPMH_CXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* suspend vote */ , , /* nominal vote */ , , /* svs vote */ , ; dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = <0 133 0>; usb-phy = <&usb2_phy0>, <&usb_nop_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; usb-core-id = <0>; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; }; qcom,usbbam@a704000 { compatible = "qcom,usb-bam-msm"; reg = <0xa704000 0x17000>; interrupts = <0 132 0>; qcom,usb-bam-fifo-baseaddr = <0x146bb000>; qcom,usb-bam-num-pipes = <4>; qcom,disable-clk-gating; qcom,usb-bam-override-threshold = <0x4001>; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x6064000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0x1800>; qcom,descriptor-fifo-offset = <0x1800>; qcom,descriptor-fifo-size = <0x800>; }; }; }; /* Primary USB port related High Speed PHY */ usb2_phy0: hsphy@88e2000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e2000 0x110>; reg-names = "hsusb_phy_base"; vdd-supply = <&pm8150_2_l5>; vdda18-supply = <&pm8150_1_l12>; vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; /* Secondary USB port related controller */ usb1: ssusb@a800000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x0a800000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x160 0x0>; qcom,smmu-s1-bypass; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 491 0>, <0 135 0>, <0 520 0>, <0 490 0>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_sec_gdsc>; clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, <&clock_rpmh RPMH_CXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; qcom,msm-bus,name = "usb1"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* suspend vote */ , , /* nominal vote */ , , /* svs vote */ , ; status = "disabled"; dwc3@a800000 { compatible = "snps,dwc3"; reg = <0x0a800000 0xcd00>; interrupts = <0 138 0>; usb-phy = <&usb2_phy1>, <&usb_nop_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; usb-core-id = <1>; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; }; }; /* Secondary USB port related High Speed PHY */ usb2_phy1: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e3000 0x110>; reg-names = "hsusb_phy_base"; vdd-supply = <&pm8150_2_l5>; vdda18-supply = <&pm8150_1_l12>; vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; status = "disabled"; }; /* Tertiary USB port related controller */ usb2: ssusb@a400000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x0a400000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x60 0x0>; qcom,smmu-s1-bypass; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 539 0>, <0 487 0>, <0 526 0>, <0 551 0>, <0 510 0>, <0 548 0>; interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq1", "ss_phy_irq1", "dm_hs_phy_irq1"; qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_mp_gdsc>; clocks = <&clock_gcc GCC_USB30_MP_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_MP_AXI_CLK>, <&clock_gcc GCC_USB30_MP_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_MP_SLEEP_CLK>, <&clock_rpmh RPMH_CXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_MP_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; qcom,charging-disabled; qcom,dual-port; qcom,msm-bus,name = "usb2"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = /* suspend vote */ , /* nominal vote */ , /* svs vote */ ; status = "disabled"; dwc3@a400000 { compatible = "snps,dwc3"; reg = <0x0a400000 0xcd00>; interrupts = <0 654 0>; usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, <&usb2_phy3>, <&usb_qmp_phy1>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; snps,usb3-u1u2-disable; snps,dis_u3_susphy_quirk; usb-core-id = <2>; maximum-speed = "super-speed-plus"; dr_mode = "host"; }; }; /* Tertiary USB port 0 related High Speed PHY */ usb2_phy2: hsphy@88e4000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e4000 0x110>; reg-names = "hsusb_phy_base"; vdd-supply = <&pm8150_2_l5>; vdda18-supply = <&pm8150_1_l12>; vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&clock_gcc GCC_QUSB2PHY_MP0_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; status = "disabled"; }; /* Tertiary USB port 0 related QMP PHY */ usb_qmp_phy0: ssphy@88eb000 { compatible = "qcom,usb-ssphy-qmp-v2"; reg = <0x88eb000 0x1000>, <0x088eb88c 0x4>; reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; vdd-supply = <&pm8150_1_l9>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&pm8150_2_l16>; qcom,qmp-phy-init-seq = /* */ ; qcom,qmp-phy-reg-offset = ; clocks = <&clock_gcc GCC_USB3_MP_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, <&clock_gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&clock_gcc GCC_USB3_UNIPHY_MP0_BCR>, <&clock_gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; reset-names = "phy_reset", "phy_phy_reset"; status = "disabled"; }; /* Tertiary USB port 1 related High Speed PHY */ usb2_phy3: hsphy@88e5000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e5000 0x110>; reg-names = "hsusb_phy_base"; vdd-supply = <&pm8150_2_l5>; vdda18-supply = <&pm8150_1_l12>; vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; resets = <&clock_gcc GCC_QUSB2PHY_MP1_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; status = "disabled"; }; /* Tertiary USB port 1 related QMP PHY */ usb_qmp_phy1: ssphy@88ec000 { compatible = "qcom,usb-ssphy-qmp-v2"; reg = <0x88ec000 0x1000>, <0x088ec88c 0x4>; reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; vdd-supply = <&pm8150_1_l9>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&pm8150_2_l16>; qcom,qmp-phy-init-seq = /* */ ; qcom,qmp-phy-reg-offset = ; clocks = <&clock_gcc GCC_USB3_MP_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, <&clock_gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <&clock_gcc GCC_USB3_UNIPHY_MP1_BCR>, <&clock_gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; reset-names = "phy_reset", "phy_phy_reset"; status = "disabled"; }; };