/*
 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/mdss-12nm-pll-clk.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
#include <dt-bindings/clock/qcom,cpu-sdm.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

/ {
	model = "Qualcomm Technologies, Inc. SDM429";
	compatible = "qcom,sdm429";
	qcom,msm-id = <416 0x0>;
	interrupt-parent = <&wakegic>;

	chosen {
		bootargs = "sched_enable_hmp=1 kpti=0";
	};

	firmware: firmware {
	     android {
		compatible = "android,firmware";
		vbmeta {
		   compatible = "android,vbmeta";
		   parts = "vbmeta,boot,system,vendor,dtbo,recovery";
		};

		fstab {
		   compatible = "android,fstab";
		   vendor {
		      compatible = "android,vendor";
		      dev =
			"/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
		      type = "ext4";
		      mnt_flags = "ro,barrier=1,discard";
		      fsmgr_flags = "wait,avb";
		      status = "ok";
		   };
		};
	     };
	  };

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		other_ext_mem: other_ext_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x85b00000 0x0 0xd00000>;
		};

		modem_mem: modem_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86800000 0x0 0x5000000> ;
		};

		adsp_fw_mem: adsp_fw_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x8b800000 0x0 0x1500000>;
		};

		wcnss_fw_mem: wcnss_fw_region@0 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x8cd00000 0x0 0x700000>;
		};


		venus_mem: venus_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
			alignment = <0 0x400000>;
			size = <0 0x0800000>;
		};

		secure_mem: secure_region@0 {
			alignment = <0 0x400000>;
			size = <0 0x800000>;
			status = "okay";
		};

		qseecom_mem: qseecom_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		adsp_mem: adsp_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		cont_splash_mem: splash_region@83000000 {
			reg = <0x0 0x90000000 0x0 0x1400000>;
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x400000>;
		};

		gpu_mem: gpu_region@0 {
			compatible = "shared-dma-pool";
			reusable;
			alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xa0000000>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
			linux,cma-default;
		};

	};

	qcom_seecom: qseecom@85b00000 {
		compatible = "qcom,qseecom";
		reg = <0x85b00000 0x800000>;
		reg-names = "secapp-region";
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,support-fde;
		qcom,commonlib64-loaded-by-uefi;
		qcom,support-bus-scaling;
		qcom,msm-bus,name = "qseecom-noc";
		qcom,msm-bus,num-cases = <4>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		   <55 512 0 0>,
		   <55 512 0 0>,
		   <55 512 120000 1200000>,
		   <55 512 393600 3936000>;
		clocks = <&gcc CRYPTO_CLK_SRC>,
		       <&gcc GCC_CRYPTO_CLK>,
		       <&gcc GCC_CRYPTO_AHB_CLK>,
		       <&gcc GCC_CRYPTO_AXI_CLK>;
		clock-names = "core_clk_src", "core_clk",
		   "iface_clk", "bus_clk";
		qcom,ce-opp-freq = <100000000>;
	};

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 for SD card */
	};

	soc: soc { };

};

#include "sdm429-bus.dtsi"
#include "sdm429-pm.dtsi"
#include "sdm429-pinctrl.dtsi"
#include "sdm429-blsp.dtsi"
#include "sdm429-cpu.dtsi"
#include "sdm429-ion.dtsi"
#include "msm-arm-smmu-sdm429.dtsi"
#include "sdm429w-gpu.dtsi"
#include "sdm429-vidc.dtsi"
&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@b000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-parent = <&intc>;
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x0b000000 0x1000>,
		      <0x0b002000 0x1000>;
	};

	wakegic: wake-gic {
		compatible = "qcom,mpm-gic-sdm429", "qcom,mpm-gic";
		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
		reg = <0x601d0 0x1000>,
			<0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
		reg-names = "vmpm", "ipc";
		qcom,num-mpm-irqs = <64>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <3>;
	};

	wakegpio: wake-gpio {
		compatible = "qcom,mpm-gpio-sdm429", "qcom,mpm-gpio";
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <2>;
	};


	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 2 0xff08>,
			     <1 3 0xff08>,
			     <1 4 0xff08>,
			     <1 1 0xff08>;
		clock-frequency = <19200000>;
	};

	timer@b120000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0xb120000 0x1000>;
		clock-frequency = <19200000>;

		frame@b121000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 7 0x4>;
			reg = <0xb121000 0x1000>,
			      <0xb122000 0x1000>;
		};

		frame@b123000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0xb123000 0x1000>;
			status = "disabled";
		};

		frame@b124000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0xb124000 0x1000>;
			status = "disabled";
		};

		frame@b125000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0xb125000 0x1000>;
			status = "disabled";
		};

		frame@b126000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0xb126000 0x1000>;
			status = "disabled";
		};

		frame@b127000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0xb127000 0x1000>;
			status = "disabled";
		};

		frame@b128000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0xb128000 0x1000>;
			status = "disabled";
		};
	};


	restart@4ab000 {
		compatible = "qcom,pshold";
		reg = <0x4ab000 0x4>,
			<0x193d100 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	clocks {
		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};
	};

	rpmcc: qcom,rpmcc {
		compatible = "qcom,rpmcc-sdm429w";
		#clock-cells = <1>;
	};

	gcc: qcom,gcc@1800000 {
		compatible = "qcom,gcc-sdm429w", "syscon";
		reg = <0x1800000 0x80000>;
		reg-names = "cc_base";
		qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	debugcc: qcom,cc-debug {
		compatible = "qcom,debugcc-sdm429w";
		qcom,gcc = <&gcc>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "xo_clk_src";
		#clock-cells = <1>;
	};

	gcc_mdss: qcom,gcc-mdss@1800000 {
		compatible = "qcom,gcc-mdss-sdm429w";
		reg = <0x1800000 0x80000>;
		clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
		       <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
		       <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
		       <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
		clock-names = "pclk0_src", "byte0_src", "pclk1_src",
			"byte1_src";
		#clock-cells = <1>;
	};

	cpu: qcom,clock-cpu@b011050 {
		compatible = "qcom,cpu-clock-sdm";
		reg =   <0xb011050 0x8>,
			<0xb1d1050 0x8>,
			<0xB016000 0x34>,
			<0x00a412c 0x8>,
			<0x0b011200 0x100>;
		reg-names = "apcs-c1-rcg-base",
			"apcs-cci-rcg-base", "apcs_pll", "efuse",
			"spm_c1_base";
		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
			<&gcc GPLL0_AO_OUT_MAIN>;
		clock-names = "xo_ao", "gpll0_ao" ;
		cpu-vdd-supply = <&apc_vreg_corner>;
		vdd_hf_pll-supply = <&L12A_AO>;
		vdd_dig_ao-supply = <&VDD_CX_LEVEL_AO>;
		qcom,speed0-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1958400000 5>;

		qcom,speed0-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed1-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1804800000 5>;

		qcom,speed1-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed4-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>,
			< 1958400000 5>,
			< 2016000000 6>;

		qcom,speed4-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		qcom,speed5-bin-v0-c1 =
			<          0 0>,
			<  960000000 1>,
			< 1305600000 1>,
			< 1497600000 2>,
			< 1708800000 3>;

		qcom,speed5-bin-v0-cci =
			<          0 0>,
			<  400000000 1>,
			<  533333333 3>;

		#clock-cells = <1>;
	};

	cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <1 7 0xff00>;
	};

	qcom,memshare {
		compatible = "qcom,memshare";

		qcom,client_1 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x200000>;
			qcom,client-id = <0>;
			qcom,allocate-boot-time;
			label = "modem";
		};

		qcom,client_2 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <2>;
			label = "modem";
		};

		mem_client_3_size: qcom,client_3 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <1>;
			qcom,allocate-on-request;
			label = "modem";
		};
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	blsp1_uart2: serial@78b0000 {
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b0000 0x200>;
		interrupts = <0 108 0>;
		clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
			<&gcc GCC_BLSP1_AHB_CLK>;
		clock-names = "core", "iface";
		status = "okay";
	};

	qcom,wdt@b017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xb017000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <0 3 0>, <0 4 0>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9360>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
		qcom,scandump-size = <0x40000>;
	};

	rpm_bus: qcom,rpm-smd {
		compatible = "qcom,rpm-smd";
		rpm-channel-name = "rpm_requests";
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		rpm-channel-type = <15>; /* SMD_APPS_RPM */
	};

	qcom,chd {
		compatible = "qcom,core-hang-detect";
		qcom,threshold-arr = <0xb088094 0xb098094 0xb0a8094
			0xb0b8094 0xb188094 0xb198094 0xb1a8094 0xb1a8094>;
		qcom,config-arr = <0xb08809c 0xb09809c 0xb0a809c
			0xb0b809c 0xb18809c 0xb19809c 0xb1a809c 0xb1b809c>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */
	};

	qcom,rmtfs_sharedmem@00000000 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x00000000 0x00180000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
	};

	sdhc_1: sdhci@7824900 {
		compatible = "qcom,sdhci-msm";
		reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>,
			<0x7803000 0x8000>;
		reg-names = "hc_mem", "core_mem", "cmdq_mem", "cmdq_ice";

		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <8>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
						 192000000 384000000>;
		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

		qcom,devfreq,freq-table = <50000000 200000000>;

		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <9>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
			<78 512 1046 3200>,    /* 400 KB/s*/
			<78 512 52286 160000>, /* 20 MB/s */
			<78 512 65360 200000>, /* 25 MB/s */
			<78 512 130718 400000>, /* 50 MB/s */
			<78 512 130718 400000>, /* 100 MB/s */
			<78 512 261438 800000>, /* 200 MB/s */
			<78 512 261438 800000>, /* 400 MB/s */
			<78 512 1338562 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000
			50000000 100000000 200000000 400000000 4294967295>;

		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
		clock-names = "iface_clk", "core_clk", "ice_core_clk";

		qcom,scaling-lower-bus-speed-mode = "DDR52";

		 /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040874>;

		qcom,nonremovable;
		status = "disabled";
	};

	sdhc_2: sdhci@7864900 {
		compatible = "qcom,sdhci-msm";
		reg = <0x7864900 0x500>, <0x7864000 0x800>;
		reg-names = "hc_mem", "core_mem";

		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
					 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <4>;
		qcom,large-address-bus;

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
								200000000>;
		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
					"SDR104";
		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <8>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
			<81 512 1046 3200>,    /* 400 KB/s*/
			<81 512 52286 160000>, /* 20 MB/s */
			<81 512 65360 200000>, /* 25 MB/s */
			<81 512 130718 400000>, /* 50 MB/s */
			<81 512 261438 800000>, /* 100 MB/s */
			<81 512 261438 800000>, /* 200 MB/s */
			<81 512 1338562 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
			100000000 200000000 4294967295>;

		qcom,devfreq,freq-table = <50000000 200000000>;
		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface_clk", "core_clk";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040874>;

		status = "disabled";
	};


	qcom,mpm2-sleep-counter@4a3000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0x4a3000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-imem@8600000 {
		compatible = "qcom,msm-imem";
		reg = <0x08600000 0x1000>; /* Address and size of IMEM */
		ranges = <0x0 0x08600000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 8>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 4>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 32>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 12>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 200>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 200>;
		};
	};

	 mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <0x85>;

		rpm_sw_dump {
			qcom,dump-size = <0x28000>;
			qcom,dump-id = <0xea>;
		};

		pmic_dump {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xe4>;
		};

		vsense_dump {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe9>;
		};

		tmc_etf_dump {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xf0>;
		};

		 tmc_etr_reg_dump {
			 qcom,dump-size = <0x1000>;
			 qcom,dump-id = <0x100>;
		 };

		 tmc_etf_reg_dump {
			 qcom,dump-size = <0x1000>;
			 qcom,dump-id = <0x101>;
		};

		 misc_data_dump {
			 qcom,dump-size = <0x1000>;
			 qcom,dump-id = <0xe8>;
		 };
	};

	qcom,lpass@c000000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xc000000 0x00100>;

		vdd_cx-supply = <&pm660_s2_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>,
			<&gcc GCC_CRYPTO_CLK>,
			<&gcc GCC_CRYPTO_AHB_CLK>,
			<&gcc GCC_CRYPTO_AXI_CLK>,
			<&gcc CRYPTO_CLK_SRC>;

		qcom,scm_core_clk_src-freq = <80000000>;
		clock-names = "xo", "scm_core_clk", "scm_iface_clk",
			"scm_bus_clk", "scm_core_clk_src";
		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
			"scm_bus_clk", "scm_core_clk_src";

		qcom,pas-id = <1>;
		qcom,mas-crypto = <&mas_crypto>;
		qcom,complete-ramdump;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";

		/* GPIO inputs from lpass */
		interrupts-extended = <&intc 0 293 1>,
				<&adsp_smp2p_in 0 0>,
				<&adsp_smp2p_in 2 0>,
				<&adsp_smp2p_in 1 0>,
				<&adsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack";
		/* GPIO output to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
		memory-region = <&adsp_fw_mem>;
	};

	qcom,pronto@a21b000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x0a21b000 0x3000>;

		vdd_pronto_pll-supply = <&pm660_l12>;
		qcom,proxy-reg-names = "vdd_pronto_pll";
		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,
			<&gcc GCC_CRYPTO_CLK>,
			<&gcc GCC_CRYPTO_AHB_CLK>,
			<&gcc GCC_CRYPTO_AXI_CLK>,
			<&gcc CRYPTO_CLK_SRC>;
		clock-names = "xo", "scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";
		qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
					"scm_bus_clk", "scm_core_clk_src";
		qcom,pas-id = <6>;
		qcom,mas-crypto = <&mas_crypto>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <422>;
		qcom,sysmon-id = <6>;
		qcom,ssctl-instance-id = <0x13>;
		qcom,firmware-name = "wcnss";

		/* GPIO inputs from wcnss */
		interrupts-extended = <&intc 0 149 1>,
				<&wcnss_smp2p_in 0 0>,
				<&wcnss_smp2p_in 2 0>,
				<&wcnss_smp2p_in 1 0>,
				<&wcnss_smp2p_in 3 0>,
				<&wcnss_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack",
				"qcom,shutdown-ack";

		/* GPIO output to wcnss */
		qcom,smem-states = <&wcnss_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";
		memory-region = <&wcnss_fw_mem>;
	};
	qcom,venus@1de0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x1de0000 0x4000>;

		vdd-supply = <&venus_gdsc>;
		qcom,proxy-reg-names = "vdd";

		clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
			 <&gcc GCC_VENUS0_AHB_CLK>,
			 <&gcc GCC_VENUS0_AXI_CLK>,
			 <&gcc GCC_CRYPTO_CLK>,
			 <&gcc GCC_CRYPTO_AHB_CLK>,
			 <&gcc GCC_CRYPTO_AXI_CLK>,
			 <&gcc CRYPTO_CLK_SRC>;

		clock-names = "core_clk", "iface_clk", "bus_clk",
				"scm_core_clk", "scm_iface_clk",
				"scm_bus_clk", "scm_core_clk_src";

		qcom,proxy-clock-names = "core_clk", "iface_clk",
					 "bus_clk", "scm_core_clk",
					 "scm_iface_clk", "scm_bus_clk",
					 "scm_core_clk_src";
		qcom,scm_core_clk_src-freq = <80000000>;

		qcom,msm-bus,name = "pil-venus";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<63 512 0 0>,
				<63 512 0 304000>;

		qcom,mas-crypto = <&mas_crypto>;
		qcom,pas-id = <9>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&venus_mem>;
	};
	pil_modem: qcom,mss@4080000 {
		compatible = "qcom,pil-q6v55-mss";
		reg =   <0x4080000 0x100>,
			<0x0194f000 0x010>,
			<0x01950000 0x008>,
			<0x01951000 0x008>,
			<0x04020000 0x040>,
			<0x01871000 0x004>;
		reg-names = "qdsp6_base", "halt_q6", "halt_modem",
			"halt_nc", "rmb_base", "restart_reg",
			"cxip_lm_vote_clear";

		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>,
			<&gcc GCC_MSS_CFG_AHB_CLK>,
			<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
			<&gcc GCC_BOOT_ROM_AHB_CLK>;
		clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
		qcom,proxy-clock-names = "xo";
		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";

		vdd_mss-supply = <&S6A>;
		vdd_cx-supply = <&pm660_s1_level_ao>;
		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
		vdd_mx-supply = <&pm660_s2_level_ao>;
		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
		vdd_pll-supply = <&L12A>;
		qcom,vdd_pll = <1800000>;
		vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;

		qcom,pas-id = <5>;
		qcom,pil-mss-memsetup;
		qcom,firmware-name = "modem";
		qcom,pil-self-auth;
		qcom,sequential-fw-load;
		qcom,override-acc-1 = <0x80800000>;
		qcom,sysmon-id = <0>;
		qcom,ssctl-instance-id = <0x12>;
		memory-region = <&modem_mem>;
		qcom,qdsp6v56-1-8-inrush-current;
		qcom,reset-clk;

		/* Inputs from mss */
		interrupts-extended = <&intc 0 24 1>,
				<&modem_smp2p_in 0 0>,
				<&modem_smp2p_in 2 0>,
				<&modem_smp2p_in 1 0>,
				<&modem_smp2p_in 3 0>,
				<&modem_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
			"qcom,err-fatal",
			"qcom,proxy-unvote",
			"qcom,err-ready",
			"qcom,stop-ack",
			"qcom,shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		status = "ok";
	};

	rpm_bus: qcom,rpm-smd { };

	usb_otg: usb@78db000 {
		compatible = "qcom,hsusb-otg";
		reg = <0x78db000 0x400>, <0x6c000 0x200>;
		reg-names = "core", "phy_csr";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <0 134 0>,<0 140 0>;
		interrupt-names = "core_irq", "async_irq";

		hsusb_vdd_dig-supply = <&L6A>;
		HSUSB_1p8-supply = <&L12A>;
		HSUSB_3p3-supply = <&L16A>;
		qcom,vdd-voltage-level = <0 928000 928000>;

		qcom,hsusb-otg-phy-init-seq = <0x43 0x80 0x06 0x82 0xffffffff>;
		qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */
		qcom,hsusb-otg-mode = <1>; /* DEVICE mode */
		qcom,hsusb-otg-otg-control = <2>; /* PMIC */
		qcom,dp-manual-pullup;
		qcom,phy-dvdd-always-on;
		qcom,boost-sysclk-with-streaming;
		qcom,axi-prefetch-enable;
		qcom,hsusb-otg-delay-lpm;
		qcom,enumeration-check-for-sdp;

		qcom,msm-bus,name = "usb2";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<87 512 0 0>,
				<87 512 80000 0>,
				<87 512 6000  6000>;
		clocks = <&gcc GCC_USB_HS_AHB_CLK>,
			 <&gcc GCC_USB_HS_SYSTEM_CLK>,
			 <&gcc GCC_USB2A_PHY_SLEEP_CLK>,
			 <&rpmcc BIMC_USB_A_CLK>,
			 <&rpmcc SNOC_USB_A_CLK>,
			 <&rpmcc PNOC_USB_A_CLK>,
			 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
			 <&rpmcc CXO_SMD_OTG_CLK>;
		clock-names = "iface_clk", "core_clk", "sleep_clk",
				"bimc_clk", "snoc_clk", "pcnoc_clk",
				"phy_csr_clk", "xo";
		qcom,bus-clk-rate = <748800000 200000000 100000000>;
		qcom,max-nominal-sysclk-rate = <133330000>;

		resets = <&gcc GCC_USB_HS_BCR>,
			 <&gcc GCC_QUSB2_PHY_BCR>,
			 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
		reset-names = "core_reset", "phy_reset", "phy_por_reset";

		qcom,usbbam@78c4000 {
			compatible = "qcom,usb-bam-msm";
			reg = <0x78c4000 0x17000>;
			interrupt-parent = <&intc>;
			interrupts = <0 135 0>;

			qcom,bam-type = <1>;
			qcom,usb-bam-num-pipes = <4>;
			qcom,usb-bam-fifo-baseaddr = <0x08605000>;
			qcom,ignore-core-reset-ack;
			qcom,disable-clk-gating;
			qcom,usb-bam-max-mbps-highspeed = <400>;
			qcom,reset-bam-on-disconnect;

			qcom,pipe0 {
				label = "hsusb-qdss-in-0";
				qcom,usb-bam-mem-type = <2>;
				qcom,dir = <1>;
				qcom,pipe-num = <0>;
				qcom,peer-bam = <0>;
				qcom,peer-bam-physical-address = <0x6044000>;
				qcom,src-bam-pipe-index = <0>;
				qcom,dst-bam-pipe-index = <0>;
				qcom,data-fifo-offset = <0x0>;
				qcom,data-fifo-size = <0xe00>;
				qcom,descriptor-fifo-offset = <0xe00>;
				qcom,descriptor-fifo-size = <0x200>;
			};
		};
	};

	spmi_bus: qcom,spmi@200f000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x200f000 0x1000>,
			<0x2400000 0x800000>,
			<0x2c00000 0x800000>,
			<0x3800000 0x200000>,
			<0x200a000 0x2100>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
		qcom,ee = <0>;
		qcom,channel = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-controller;
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	thermal_zones: thermal-zones { };

	tcsr_mutex_regs: syscon@1905000 {
		compatible = "syscon";
		reg = <0x1905000 0x8000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	apcs: syscon@0b011008 {
		compatible = "syscon";
		reg = <0x0b011008 0x04>;
	};

	rpm_msg_ram: memory@60000 {
		compatible = "qcom,rpm-msg-ram";
		reg = <0x60000 0x8000>;
	};

	smem_mem: smem_region@86300000 {
		reg = <0x86300000 0x100000>;
		no-map;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		hwlocks = <&tcsr_mutex 3>;
	};

	qcom,smd {
		compatible = "qcom,smd";

		modem {
			qcom,smd-edge = <0>;
			qcom,ipc = <&apcs 0 12>;
			qcom,remote-pid = <1>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
			label = "mpss";

			qcom,smd-channels = "IPCRTR";
			qcom,modem_qrtr {
				qcom,net-id = <1>;
				qcom,low-latency;
			};
		};

		wcnss {
			qcom,smd-edge = <6>;
			qcom,ipc = <&apcs 0 17>;
			qcom,remote-pid = <4>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
			label = "wcnss";

			qcom,smd-channels = "IPCRTR";
			qcom,wcnss_qrtr {
				qcom,net-id = <1>;
				qcom,low-latency;
			};

			qcom,diag {
				qcom,smd-channels = "APPS_RIVA_DATA";
			};
			qcom,diag_cntl {
				qcom,smd-channels = "APPS_RIVA_CTRL";
			};
		};

		adsp {
			qcom,smd-edge = <1>;
			qcom,ipc = <&apcs 0 8>;
			qcom,remote-pid = <2>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			label = "adsp";

			qcom,smd-channels = "IPCRTR";
			qcom,adsp_qrtr {
				qcom,net-id = <1>;
				qcom,low-latency;
			};
			qcom,apr_tal_rpmsg {
				qcom,smd-channels = "apr_audio_svc";
			};
		};

		rpm {
			qcom,smd-edge = <15>;
			qcom,ipc = <&apcs 0 0>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			label = "rpm";

			rpm_requests: rpm_requests@0 {
				compatible = "qcom,rpm-smd";
				qcom,smd-channels = "rpm_requests";
			};
		};
	};

	qcom,smsm {
		compatible = "qcom,smsm";
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 0 13>;
		qcom,ipc-2 = <&apcs 0 9>;
		qcom,ipc-3 = <&apcs 0 19>;

		apps_smsm: apps@0 {
			reg = <0>;
			#qcom,smem-state-cells = <1>;
		};

		modem_smsm: modem@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		adsp_smsm: adsp@2 {
			reg = <2>;
			interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@3 {
			reg = <3>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	modem-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	adsp-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,adsprpc-mem {
	compatible = "qcom,msm-adsprpc-mem-region";
	memory-region = <&adsp_mem>;
	restrict-access;
	};

	qcom,msm_fastrpc {
		compatible ="qcom,msm-fastrpc-legacy-compute";
		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-legacy-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_iommu 0x2008 0x7>;
			sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
		};
	};

	wcnss-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smdpkt {
		compatible = "qcom,smdpkt";

		qcom,smdpkt-data5-cntl {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA5_CNTL";
			qcom,smdpkt-dev-name = "smdcntl0";
		};

		qcom,smdpkt-data22 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA22";
			qcom,smdpkt-dev-name = "smd22";
		};

		qcom,smdpkt-data40-cntl {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA40_CNTL";
			qcom,smdpkt-dev-name = "smdcntl8";
		};

		qcom,smdpkt-data2 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA2";
			qcom,smdpkt-dev-name = "at_mdm0";
		};

		qcom,smdpkt-apr-apps2 {
			qcom,smdpkt-edge = "adsp";
			qcom,smdpkt-ch-name = "apr_apps2";
			qcom,smdpkt-dev-name = "apr_apps2";
		};

		qcom,smdpkt-apps-fm {
			qcom,smdpkt-edge = "wcnss";
			qcom,smdpkt-ch-name = "APPS_FM";
			qcom,smdpkt-dev-name = "smd1";
		};

		qcom,smdpkt-apps-riva-bt-acl {
			qcom,smdpkt-edge = "wcnss";
			qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL";
			qcom,smdpkt-dev-name = "smd2";
		};

		qcom,smdpkt-apps-riva-bt-cmd {
			qcom,smdpkt-edge = "wcnss";
			qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD";
			qcom,smdpkt-dev-name = "smd3";
		};

		qcom,smdpkt-mbalbridge {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "MBALBRIDGE";
			qcom,smdpkt-dev-name = "smd4";
		};

		qcom,smdpkt-apps-riva-ant-cmd {
			qcom,smdpkt-edge = "wcnss";
			qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD";
			qcom,smdpkt-dev-name = "smd5";
		};

		qcom,smdpkt-apps-riva-ant-data {
			qcom,smdpkt-edge = "wcnss";
			qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA";
			qcom,smdpkt-dev-name = "smd6";
		};

		qcom,smdpkt-data1 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA1";
			qcom,smdpkt-dev-name = "smd7";
		};

		qcom,smdpkt-data4 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA4";
			qcom,smdpkt-dev-name = "smd8";
		};

		qcom,smdpkt-data11 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA11";
			qcom,smdpkt-dev-name = "smd11";
		};

		qcom,smdpkt-data21 {
			qcom,smdpkt-edge = "modem";
			qcom,smdpkt-ch-name = "DATA21";
			qcom,smdpkt-dev-name = "smd21";
		};
	};

	qcom_tzlog: tz-log@08600720 {
		compatible = "qcom,tz-log";
		reg = <0x08600720 0x2000>;
	};

	qcom_crypto: qcrypto@720000 {
		compatible = "qcom,qcrypto";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 207 0>;
		qcom,bam-pipe-pair = <2>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,clk-mgmt-sus-res;
		qcom,msm-bus,name = "qcrypto-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<55 512 0 0>,
			<55 512 393600 393600>;
		clocks = <&gcc CRYPTO_CLK_SRC>,
			<&gcc GCC_CRYPTO_CLK>,
			<&gcc GCC_CRYPTO_AHB_CLK>,
			<&gcc GCC_CRYPTO_AXI_CLK>;
		clock-names = "core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		qcom,use-sw-aes-cbc-ecb-ctr-algo;
		qcom,use-sw-aes-xts-algo;
		qcom,use-sw-aes-ccm-algo;
		qcom,use-sw-ahash-algo;
		qcom,use-sw-hmac-algo;
		qcom,use-sw-aead-algo;
		qcom,ce-opp-freq = <100000000>;
	};

	qcom_cedev: qcedev@720000 {
		compatible = "qcom,qcedev";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 207 0>;
		qcom,bam-pipe-pair = <1>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,msm-bus,name = "qcedev-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<55 512 0 0>,
			<55 512 393600 393600>;
		clocks = <&gcc CRYPTO_CLK_SRC>,
			<&gcc GCC_CRYPTO_CLK>,
			<&gcc GCC_CRYPTO_AHB_CLK>,
			<&gcc GCC_CRYPTO_AXI_CLK>;
		clock-names = "core_clk_src", "core_clk",
			"iface_clk", "bus_clk";
		qcom,ce-opp-freq = <100000000>;
	};

	qcom_rng: qrng@e3000 {
		compatible = "qcom,msm-rng";
		reg = <0xe3000 0x1000>;
		qcom,msm-rng-iface-clk;
		qcom,no-qrng-config;
		qcom,msm-bus,name = "msm-rng-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<1 618 0 0>,            /* No vote */
			<1 618 0 800>;          /* 100 MB/s */
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
		clock-names = "iface_clk";
	};

	qcom,wcnss-wlan@0a000000 {
		compatible = "qcom,wcnss_wlan";
		reg = <0x0a000000 0x280000>,
		      <0xb011008 0x04>,
		      <0x0a21b000 0x3000>,
		      <0x03204000 0x00000100>,
		      <0x03200800 0x00000200>,
		      <0x0a100400 0x00000200>,
		      <0x0a205050 0x00000200>,
		      <0x0a219000 0x00000020>,
		      <0x0a080488 0x00000008>,
		      <0x0a080fb0 0x00000008>,
		      <0x0a08040c 0x00000008>,
		      <0x0a0120a8 0x00000008>,
		      <0x0a012448 0x00000008>,
		      <0x0a080c00 0x00000001>;

		reg-names = "wcnss_mmio", "wcnss_fiq",
			    "pronto_phy_base", "riva_phy_base",
			    "riva_ccu_base", "pronto_a2xb_base",
			    "pronto_ccpu_base", "pronto_saw2_base",
			    "wlan_tx_phy_aborts","wlan_brdg_err_source",
			    "wlan_tx_status", "alarms_txctl",
			    "alarms_tactl", "pronto_mcu_base";

		interrupts = <0 145 0 0 146 0>;
		interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";

		qcom,pronto-vddmx-supply = <&pm660_s2_level_ao>;
		qcom,pronto-vddcx-supply = <&pm660_s1_level>;
		qcom,pronto-vddpx-supply = <&pm660_l13>;
		qcom,iris-vddxo-supply   = <&pm660_l12>;
		qcom,iris-vddrfa-supply  = <&pm660_l5>;
		qcom,iris-vdddig-supply  = <&pm660_l13>;

		qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
		qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
		qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
		qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;

		qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO
					RPM_SMD_REGULATOR_LEVEL_NONE
					RPM_SMD_REGULATOR_LEVEL_TURBO>;
		qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
					RPM_SMD_REGULATOR_LEVEL_NONE
					RPM_SMD_REGULATOR_LEVEL_BINNING>;
		qcom,vddpx-voltage-level = <1800000 0 1800000>;

		qcom,iris-vddxo-current = <10000>;
		qcom,iris-vddrfa-current = <100000>;
		qcom,iris-vddpa-current = <515000>;
		qcom,iris-vdddig-current = <10000>;

		qcom,pronto-vddmx-current = <0>;
		qcom,pronto-vddcx-current = <0>;
		qcom,pronto-vddpx-current = <0>;

		pinctrl-names = "wcnss_default", "wcnss_sleep",
				"wcnss_gpio_default";
		pinctrl-0 = <&wcnss_default>;
		pinctrl-1 = <&wcnss_sleep>;
		pinctrl-2 = <&wcnss_gpio_default>;

		gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>,
			<&tlmm 79 0>, <&tlmm 80 0>;

		clocks = <&rpmcc CXO_SMD_WLAN_CLK>,
			 <&rpmcc RPM_SMD_RF_CLK2>,
			 <&rpmcc SNOC_WCNSS_A_CLK>;

		clock-names = "xo", "rf_clk", "snoc_wcnss";

		qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
		qcom,smem-state-names = "tx-enable", "tx-rings-empty";

		qcom,snoc-wcnss-clock-freq = <200000000>;

		qcom,has-autodetect-xo;
		qcom,is-pronto-v3;
		qcom,has-pronto-hw;
		qcom,has-vsys-adc-channel;
	};

	bluetooth: bt_wcn3990 {
		compatible = "qca,wcn3990";
		qca,bt-3P3-en-gpio = <&tlmm 47 0>; /* WCN3980_3P3_EN_*/
		qca,bt-1P3-en-gpio = <&tlmm 57 0>; /* WCN3980_1P3_EN */

		qca,bt-vdd-xtal-supply = <&pm660_l12>;
		qca,bt-vdd-io-supply = <&pm660_l13>;

		qca,bt-vdd-xtal-voltage-level = <1800000 1900000>;
		qca,bt-vdd-io-voltage-level = <1800000 1900000>;

		qca,bt-vdd-xtal-current-level = <80000>;
		qca,bt-vdd-io-current-level = <10000>;
	};

	qcom,bam_dmux@4044000 {
		compatible = "qcom,bam_dmux";
		reg = <0x4044000 0x19000>;
		qcom,rx-ring-size = <32>;
		qcom,max-rx-mtu = <4096>;
		qcom,fast-shutdown;
		qcom,no-cpu-affinity;

		qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
		qcom,smem-state-names = "pwrctrl", "pwrctrlack";

		interrupts-extended =
				<&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
				<&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>,
				<&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>;

		interrupt-names = "dmux", "ctrl", "ack";
	};

	slim_msm: slim@c140000{
		cell-index = <1>;
		compatible = "qcom,slim-ngd";
		reg = <0xc140000 0x2c000>,
			<0xc104000 0x2a000>;
		reg-names = "slimbus_physical", "slimbus_bam_physical";
		interrupts = <0 163 0>, <0 180 0>;
		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
		qcom,apps-ch-pipes = <0x600000>;
		qcom,ea-pc = <0x230>;
		status = "okay";

		/* Slimbus Slave DT for WCN3980 */
		btfmslim_codec: wcn3990 {
			compatible = "qcom,btfmslim_slave";
			elemental-addr = [00 01 20 02 17 02];
			qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
			qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
		};
	};

	qcom,msm-adsp-loader {
		status = "ok";
		compatible = "qcom,adsp-loader";
		qcom,adsp-state = <0>;
	};

	msm_cpufreq: qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clock-names = "cpu0_clk";
		clocks = <&cpu APCS_MUX_C1_CLK>;

		qcom,cpufreq-table =
			< 960000  >,
			< 1305600 >,
			< 1497600 >,
			< 1708800 >,
			< 2016000 >;
	};
	ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 211,8); /* 2265 MB/s */
		BW_OPP_ENTRY( 384, 8); /* 4539 MB/s */
		BW_OPP_ENTRY( 662, 8); /* 5416 MB/s */
		BW_OPP_ENTRY( 749, 8);
	};

	cpubw: qcom,cpubw {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	com,cpu-bwmon {
		compatible = "qcom,bimc-bwmon2";
		reg = <0x408000 0x300>, <0x401000 0x200>;
		reg-names = "base", "global_base";
		interrupts = <0 183 4>;
		qcom,mport = <0>;
		qcom,target-dev = <&cpubw>;
	};

	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_computemon: qcom,cpu0-computemon {
		compatible = "qcom,arm-cpu-mon";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
		qcom,core-dev-table =
			< 960000  MHZ_TO_MBPS( 211, 8) >,
			< 1305600 MHZ_TO_MBPS( 384, 8) >,
			< 1497600 MHZ_TO_MBPS( 662, 8) >,
			< 1708800 MHZ_TO_MBPS( 662, 8) >,
			< 2016000 MHZ_TO_MBPS( 749, 8) >;
	};

	tsens0: tsens@4a8000 {
		compatible = "qcom,msm8937-tsens";
		reg = <0x4a8000 0x1000>,
			<0x4a9000 0x1000>,
			<0xa4000  0x1000>;
		reg-names = "tsens_srot_physical",
			"tsens_tm_physical", "tsens_eeprom_physical";
		interrupts = <0 184 0>;
		interrupt-names = "tsens-upper-lower";
		#thermal-sensor-cells = <1>;
	};

	dcc: dcc@b3000 {
		compatible = "qcom,dcc";
		reg = <0xb3000 0x1000>,
		      <0xb4000 0x2000>;
		reg-names = "dcc-base", "dcc-ram-base";

		clocks = <&gcc GCC_DCC_CLK>;
		clock-names = "dcc_clk";
		qcom,save-reg;
	};

	jtag_mm0: jtagmm@61bc000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x61bc000 0x1000>;
		reg-names = "etm-base";

		qcom,coresight-jtagmm-cpu = <&CPU0>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";
	};

	jtag_mm1: jtagmm@61bd000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x61bd000 0x1000>;
		reg-names = "etm-base";

		qcom,coresight-jtagmm-cpu = <&CPU1>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";
	};

	jtag_mm2: jtagmm@61be000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x61be000 0x1000>;
		reg-names = "etm-base";

		qcom,coresight-jtagmm-cpu = <&CPU2>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";
	};

	jtag_mm3: jtagmm@61bf000 {
		compatible = "qcom,jtagv8-mm";
		reg = <0x61bf000 0x1000>;
		reg-names = "etm-base";

		qcom,coresight-jtagmm-cpu = <&CPU3>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "core_clk";
	};
};

#include "sdm429-gdsc.dtsi"
#include "sdm429w-pm660.dtsi"
#include "sdm429w-regulator.dtsi"
#include "sdm429-mdss.dtsi"
#include "sdm429-mdss-pll.dtsi"
#include "sdm429-audio.dtsi"
#include "sdm429-thermal.dtsi"
#include "sdm429-coresight.dtsi"

&venus_gdsc {
	clock-names = "bus_clk", "core_clk";
	clocks = <&gcc GCC_VENUS0_AXI_CLK>,
		<&gcc GCC_VENUS0_VCODEC0_CLK>;
	status = "ok";
};

&venus_core0_gdsc {
	qcom,support-hw-trigger;
	clock-names ="core0_clk";
	clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>;
	status = "okay";
};

&mdss_gdsc {
	clock-names = "core_clk", "bus_clk";
	clocks = <&gcc GCC_MDSS_MDP_CLK>,
		<&gcc GCC_MDSS_AXI_CLK>;
	qcom,disallow-clear;
	status = "okay";
};

&jpeg_gdsc {
	clock-names = "core_clk", "bus_clk";
	clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
		<&gcc GCC_CAMSS_JPEG_AXI_CLK>;
	status = "okay";
};

&vfe_gdsc {
	clock-names = "core_clk", "bus_clk", "micro_clk",
			"csi_clk";
	clocks = <&gcc GCC_CAMSS_VFE0_CLK>,
		<&gcc GCC_CAMSS_VFE_AXI_CLK>,
		<&gcc GCC_CAMSS_MICRO_AHB_CLK>,
		<&gcc GCC_CAMSS_CSI_VFE0_CLK>;
	status = "okay";
};

&vfe1_gdsc {
	clock-names = "core_clk", "bus_clk", "micro_clk",
			"csi_clk";
	clocks = <&gcc GCC_CAMSS_VFE1_CLK>,
		<&gcc GCC_CAMSS_VFE1_AXI_CLK>,
		<&gcc GCC_CAMSS_MICRO_AHB_CLK>,
		<&gcc GCC_CAMSS_CSI_VFE1_CLK>;
	status = "okay";
};

&cpp_gdsc {
	clock-names = "core_clk", "bus_clk";
	clocks = <&gcc GCC_CAMSS_CPP_CLK>,
		<&gcc GCC_CAMSS_CPP_AXI_CLK>;
	status = "okay";
};

&oxili_gx_gdsc {
	clock-names = "core_root_clk";
	clocks =<&gcc GFX3D_CLK_SRC>;
	qcom,enable-root-clk;
	qcom,clk-dis-wait-val = <0x5>;
	status = "okay";
};

&oxili_cx_gdsc {
	clock-names = "core_clk";
	clocks = <&gcc GCC_OXILI_GFX3D_CLK>;
	status = "okay";
};

&blsp2_uart2_hs {
	status = "okay";
};