/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "sa8195p-cnss.dtsi"

&qupv3_3 {
	status = "ok";
};

&qupv3_se0_spi {
	status = "ok";

#address-cells = <1>;
#size-cells = <0>;

	can-controller@0 {
		compatible = "qcom,nxp,mpc5746c";
		reg = <0>;
		interrupt-parent = <&tlmm>;
		interrupts = <38 0>;
		spi-max-frequency = <5000000>;
		qcom,clk-freq-mhz = <40000000>;
		qcom,max-can-channels = <1>;
		qcom,bits-per-word = <8>;
		qcom,support-can-fd;
	};
};

&qupv3_se12_2uart {
	status = "ok";
};

&qupv3_se13_4uart {
	status = "ok";
};

&qupv3_se4_i2c {
	status = "ok";
};

&pil_lpass {
	status = "ok";
};

&pil_ssc {
	status = "disabled";
};

&pil_spss {
	status = "ok";
};

&pil_turing {
	status = "ok";
};

&pil_venus {
	status = "ok";
};

&pil_npu {
	status = "ok";
};

&glink_modem {
	status = "disabled";
};

&ssc_sensors {
	status = "disabled";
};

&soc {
	qcom,msm-cdsp-loader {
		status = "ok";
	};
};

&sdhc_2 {
	vdd-supply = <&pm8195_1_l10>;
	qcom,vdd-voltage-level = <2950000 2960000>;
	qcom,vdd-current-level = <200 800000>;

	vdd-io-supply = <&pm8195_1_l2>;
	qcom,vdd-io-voltage-level = <1808000 2960000>;
	qcom,vdd-io-current-level = <200 22000>;

	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&sdc2_clk_on
		&sdc2_cmd_on &sdc2_data_on &storage_cd_default>;
	pinctrl-1 = <&sdc2_clk_off
		&sdc2_cmd_off &sdc2_data_off &storage_cd_default>;

	cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>;

	status = "ok";
};

&pcie2 {
	qcom,boot-option = <0x0>;
};

&pcie_rc2 {
nvme_x8: qcom,nvme@pcie_rc2 {
		 reg = <0 0 0 0 0>;
		 compatible = "qcom,nvme";
		 pci-ids =
			 "8086:0953",
			 "8086:0a54",
			 "8086:0a55",
			 "8086:f1a5",
			 "8086:f1a5",
			 "1c58:0003",
			 "1c58:0023",
			 "1c5c:1327",
			 "1c5f:0540",
			 "144d:a821",
			 "144d:a822",
			 "144d:a808",
			 "1d1d:1f1f",
			 "1d1d:2807",
			 "1d1d:2601",
			 "106b:2001",
			 "106b:2003",
			 "1179:0115",
			 "1179:0116";

		 qcom,smmu;
		 qcom,smmu-iova-base = /bits/ 64 <0x20000000>;
		 qcom,smmu-iova-size = /bits/ 64 <0x40000000>;

		 qcom,smmu-attr-atomic;
		 qcom,smmu-attr-s1-bypass;
	 };
};