/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84208>, <0xaeb0000 0x2008>, <0xaeac000 0x214>, <0xae8f000 0x02c>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "sid_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; clock-rate = <0 0 0 300000000 19200000 200000000 200000000>; clock-max-rate = <0 0 0 460000000 19200000 460000000 460000000>; /* interrupt config */ interrupts = ; interrupt-controller; #interrupt-cells = <1>; iommus = <&apps_smmu 0x800 0x2>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; /* hw blocks */ qcom,sde-off = <0x1000>; qcom,sde-len = <0x494>; qcom,sde-ctl-off = <0x2000 0x2200 0x2400>; qcom,sde-ctl-size = <0x1dc>; qcom,sde-ctl-display-pref = "primary", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000>; qcom,sde-mixer-size = <0x320>; qcom,sde-mixer-display-pref = "primary", "none"; qcom,sde-mixer-cwb-pref = "none", "cwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0x1800>; qcom,sde-wb-off = <0x66000>; qcom,sde-wb-size = <0x2c8>; qcom,sde-wb-xin-id = <6>; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x3b8 24>; qcom,sde-intf-off = <0x6b000 0x6b800>; qcom,sde-intf-size = <0x2b8>; qcom,sde-intf-type = "dp", "dsi"; qcom,sde-pp-off = <0x71000 0x71800>; qcom,sde-pp-slave = <0x0 0x0>; qcom,sde-pp-size = <0xd4>; qcom,sde-pp-merge-3d-id = <0x0 0x0>; qcom,sde-merge-3d-off = <0x84000>; qcom,sde-merge-3d-size = <0x100>; qcom,sde-te2-off = <0x2000 0x2000>; qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; qcom,sde-dither-off = <0x30e0 0x30e0>; qcom,sde-dither-version = <0x00010000>; qcom,sde-dither-size = <0x20>; qcom,sde-sspp-type = "vig", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>; qcom,sde-sspp-src-size = <0x1f8>; qcom,sde-sspp-xin-id = <0 1 5 9 >; qcom,sde-sspp-excl-rect = <1 1 1 1>; qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; qcom,sde-mixer-pair-mask = <2 1>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000 2600000 2600000>; qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000 2600000 2600000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 8>, <0x2ac 8>, <0x2c4 8>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-type = "qseedv3lite"; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2160>; qcom,sde-vig-sspp-linewidth = <4096>; qcom,sde-wb-linewidth = <1920>; qcom,sde-mixer-blendstages = <0x7>; qcom,sde-highest-bank-bit = <0x1>; qcom,sde-ubwc-version = <0x200>; qcom,sde-ubwc-bw-calc-version = <0x1>; qcom,sde-ubwc-static = <0x1E>; qcom,sde-panic-per-pipe; qcom,sde-smart-panel-align-mode = <0xc>; qcom,sde-has-cdp; qcom,sde-has-src-split; qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; qcom,sde-has-idle-pc; qcom,sde-max-bw-low-kbps = <3900000>; qcom,sde-max-bw-high-kbps = <5500000>; qcom,sde-min-core-ib-kbps = <2400000>; qcom,sde-min-llcc-ib-kbps = <800000>; qcom,sde-min-dram-ib-kbps = <800000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; qcom,sde-vbif-off = <0>; qcom,sde-vbif-size = <0x1040>; qcom,sde-vbif-id = <0>; qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; /* macrotile & macrotile-qseed has the same configs */ qcom,sde-danger-lut = <0x000000ff 0x0000ffff 0x00000000 0x00000000 0x0000ffff>; qcom,sde-safe-lut-linear = <0 0xfff0>; qcom,sde-safe-lut-macrotile = <0 0xff00>; /* same as safe-lut-macrotile */ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; qcom,sde-safe-lut-nrt = <0 0xffff>; qcom,sde-safe-lut-cwb = <0 0x3ff>; qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; qcom,sde-cdp-setting = <1 1>, <1 0>; qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0>; qcom,sde-reg-dma-version = <0x00010002>; qcom,sde-reg-dma-trigger-off = <0x119c>; qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; qcom,sde-secure-sid-mask = <0x801>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; qcom,sde-vig-gamut = <0x1d00 0x00060000>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; qcom,sde-sspp-dma-blocks { dgm@0 { qcom,sde-dma-igc = <0x400 0x00050000>; qcom,sde-dma-gc = <0x600 0x00050000>; qcom,sde-dma-inverse-pma; qcom,sde-dma-csc-off = <0x200>; }; dgm@1 { qcom,sde-dma-igc = <0x1400 0x00050000>; qcom,sde-dma-gc = <0x600 0x00050000>; qcom,sde-dma-inverse-pma; qcom,sde-dma-csc-off = <0x1200>; }; }; qcom,sde-dspp-blocks { qcom,sde-dspp-igc = <0x0 0x00030001>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; qcom,sde-dspp-gamut = <0x1000 0x00040002>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; }; /* data and reg bus scale settings */ qcom,sde-data-bus { qcom,msm-bus,name = "mdss_sde"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <22 512 0 6400000>, <22 512 0 6400000>; }; qcom,sde-reg-bus { qcom,msm-bus,name = "mdss_reg"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>, <1 590 0 150000>, <1 590 0 300000>; }; qcom,sde-limits { qcom,sde-linewidth-limits{ qcom,sde-limit-name = "sspp_linewidth_usecases"; qcom,sde-limit-cases = "vig", "dma", "scale"; qcom,sde-limit-ids= <0x1 0x2 0x4>; qcom,sde-limit-values = <0x1 4096>, <0x5 2560>, <0x2 2160>; }; qcom,sde-bw-limits{ qcom,sde-limit-name = "sde_bwlimit_usecases"; qcom,sde-limit-cases = "per_vig_pipe", "per_dma_pipe", "total_max_bw", "camera_concurrency", "cwb_concurrency"; qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>; qcom,sde-limit-values = <0x1 2600000>, <0x11 2600000>, <0x9 2600000>, <0x19 2600000>, <0x2 2600000>, <0x12 2600000>, <0xa 2600000>, <0x1a 2600000>, <0x4 5800000>, <0x14 5500000>, <0xc 4400000>, <0x1c 3900000>; }; }; }; sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x3c50>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <3>; qcom,sde-dram-channels = <2>; mboxes = <&disp_rsc 0>; mbox-names = "disp_rsc"; vdd-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; /* data and reg bus scale settings */ qcom,sde-data-bus { qcom,msm-bus,name = "disp_rsc_mnoc"; qcom,msm-bus,active-only; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <20003 20515 0 0>, <20003 20515 0 6400000>, <20003 20515 0 6400000>; }; qcom,sde-llcc-bus { qcom,msm-bus,name = "disp_rsc_llcc"; qcom,msm-bus,active-only; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <20001 20513 0 0>, <20001 20513 0 6400000>, <20001 20513 0 6400000>; }; qcom,sde-ebi-bus { qcom,msm-bus,name = "disp_rsc_ebi"; qcom,msm-bus,active-only; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <20000 20512 0 0>, <20000 20512 0 6400000>, <20000 20512 0 6400000>; }; }; mdss_rotator: qcom,mdss_rotator@aea8800 { compatible = "qcom,sde_rotator"; reg = <0xae00000 0xac000>, <0xaeb8000 0x3000>; reg-names = "mdp_phys", "rot_vbif_phys"; #list-cells = <1>; qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x1>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <25 512 0 0>, <25 512 0 6400000>, <25 512 0 6400000>; rot-vdd-supply = <&mdss_core_gdsc>; qcom,supply-names = "rot-vdd"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "iface_clk", "rot_clk"; interrupt-parent = <&mdss_mdp>; interrupts = <2 0>; power-domains = <&mdss_mdp>; /* Offline rotator QoS setting */ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; qcom,mdss-rot-vbif-memtype = <3 3>; qcom,mdss-rot-cdp-setting = <1 1>; qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; qcom,mdss-rot-danger-lut = <0x0 0x0>; qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <32>; qcom,mdss-sbuf-headroom = <20>; /* reg bus scale settings */ rot_reg: qcom,rot-reg-bus { qcom,msm-bus,name = "mdss_rot_reg"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 590 0 0>, <1 590 0 76800>; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; iommus = <&apps_smmu 0xC1C 0x0>; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { compatible = "qcom,smmu_sde_rot_sec"; iommus = <&apps_smmu 0xC1D 0x0>; }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { compatible = "qcom,dsi-ctrl-hw-v2.4"; label = "dsi-ctrl-0"; cell-index = <0>; reg = <0xae94000 0x400>, <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; vdda-1p2-supply = <&L3C>; refgen-supply = <&refgen>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk"; qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; }; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "refgen"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-0"; cell-index = <0>; reg = <0xae94400 0x7c0>, <0xae94200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; vdda-0p9-supply = <&S3A_LEVEL>; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = [00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,panel-allow-phy-poweroff; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = ; qcom,supply-max-voltage = ; qcom,supply-off-min-voltage = ; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; sde_dp: qcom,dp_display@ae90000 { status = "ok"; cell-index = <0>; compatible = "qcom,dp-display"; vdda-1p2-supply = <&L3C>; vdda-0p9-supply = <&L4A>; reg = <0xae90000 0x200>, <0xae90200 0x200>, <0xae90400 0xc00>, <0xae91000 0x400>, <0x88eaa00 0x200>, <0x88ea200 0x200>, <0x88ea600 0x200>, <0xaf02000 0x2d0>, <0x780000 0x6228>, <0x88ea030 0x10>, <0x88e8000 0x20>, <0x0aee1000 0x2a>, <0xae91400 0x400>; reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_mmss_cc", "qfprom_physical", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1"; interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13 23 1d]; qcom,aux-cfg2-settings = [28 24]; qcom,aux-cfg3-settings = [2c 00]; qcom,aux-cfg4-settings = [30 0a]; qcom,aux-cfg5-settings = [34 26]; qcom,aux-cfg6-settings = [38 0a]; qcom,aux-cfg7-settings = [3c 03]; qcom,aux-cfg8-settings = [40 bb]; qcom,aux-cfg9-settings = [44 03]; qcom,max-pclk-frequency-khz = <337500>; qcom,max-hdisplay = <2560>; qcom,max-vdisplay = <1600>; qcom,no-mst-encoder; clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_aux_clk", "core_usb_pipe_clk", "core_usb_ref_clk_src", "core_usb_ref_clk", "core_usb_pipe_clk", "link_clk", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "strm0_pixel_clk"; qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; }; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; qcom,supply-max-voltage = <928000>; qcom,supply-enable-load = <36000>; qcom,supply-disable-load = <0>; }; }; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "refgen"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; };