/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	msm_npu: qcom,msm_npu@9800000 {
		compatible = "qcom,msm-npu";
		status = "ok";
		reg = <0x9900000 0x20000>,
			<0x99f0000 0x10000>,
			<0x9980000 0x10000>,
			<0x17c00000 0x10000>,
			<0x01f40000 0x40000>,
			<0x780000 0x7000>;
		reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
			"qfprom_physical";
		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
			"general_irq";
		iommus = <&apps_smmu 0x1441 0x0>, <&apps_smmu 0x1442 0x0>,
			<&apps_smmu 0x1461 0x0>, <&apps_smmu 0x1462 0x0>,
			<&apps_smmu 0x1481 0x0>, <&apps_smmu 0x1482 0x0>;
		qcom,npu-dsp-sid-mapped;

		clocks = <&clock_npucc NPU_CC_XO_CLK>,
			<&clock_npucc NPU_CC_CORE_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_CDC_CLK>,
			<&clock_npucc NPU_CC_NOC_AXI_CLK>,
			<&clock_npucc NPU_CC_NOC_AHB_CLK>,
			<&clock_npucc NPU_CC_NOC_DMA_CLK>,
			<&clock_npucc NPU_CC_RSC_XO_CLK>,
			<&clock_npucc NPU_CC_S2P_CLK>,
			<&clock_npucc NPU_CC_BWMON_CLK>,
			<&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
			<&clock_npucc NPU_CC_BTO_CORE_CLK>,
			<&clock_npucc NPU_DSP_CORE_CLK_SRC>;
		clock-names = "xo_clk",
			"npu_core_clk",
			"cal_hm0_clk",
			"cal_hm0_cdc_clk",
			"axi_clk",
			"ahb_clk",
			"dma_clk",
			"rsc_xo_clk",
			"s2p_clk",
			"bwmon_clk",
			"cal_hm0_perf_cnt_clk",
			"bto_core_clk",
			"dsp_core_clk_src";

		vdd-supply = <&npu_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		#cooling-cells = <2>;
		mboxes = <&apcs_glb2 4>,
			<&apcs_glb2 6>;
		mbox-names = "glink", "smp2p";
		#mbox-cells = <1>;
		qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;
		qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";
		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
			<MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
		qcom,npu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,npu-pwrlevels";
			initial-pwrlevel = <4>;
			qcom,npu-pwrlevel@0 {
				reg = <0>;
				vreg = <1>;
				clk-freq = <19200000
					100000000
					192000000
					192000000
					150000000
					30000000
					200000000
					19200000
					50000000
					19200000
					192000000
					19200000
					300000000>;
			};

			qcom,npu-pwrlevel@1 {
				reg = <1>;
				vreg = <2>;
				clk-freq = <19200000
					200000000
					268800000
					268800000
					200000000
					37500000
					300000000
					19200000
					50000000
					19200000
					268800000
					19200000
					400000000>;
			};

			qcom,npu-pwrlevel@2 {
				reg = <2>;
				vreg = <3>;
				clk-freq = <19200000
					333000000
					403200000
					403200000
					300000000
					37500000
					403000000
					19200000
					50000000
					19200000
					403200000
					19200000
					500000000>;
			};

			qcom,npu-pwrlevel@3 {
				reg = <3>;
				vreg = <4>;
				clk-freq = <19200000
					428000000
					515000000
					515000000
					403000000
					75000000
					600000000
					19200000
					100000000
					19200000
					515000000
					19200000
					660000000>;
			};

			qcom,npu-pwrlevel@4 {
				reg = <4>;
				vreg = <6>;
				clk-freq = <19200000
					500000000
					748800000
					748800000
					533000000
					75000000
					710000000
					19200000
					100000000
					19200000
					748800000
					19200000
					800000000>;
			};
		};
	};
};