208 lines
6.8 KiB
C
208 lines
6.8 KiB
C
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/*
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* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
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#define _DT_BINDINGS_CLK_MSM_GCC_660_H
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/* Hardware/Dummy/Voter clocks */
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#define GCC_XO 0
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#define GCC_GPLL0_EARLY_DIV 1
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#define GCC_GPLL1_EARLY_DIV 2
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#define GCC_CE1_AHB_M_CLK 3
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#define GCC_CE1_AXI_M_CLK 4
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/* RCGs and Branches */
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17
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#define BLSP1_UART1_APPS_CLK_SRC 18
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#define BLSP1_UART2_APPS_CLK_SRC 19
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27
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#define BLSP2_UART1_APPS_CLK_SRC 28
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#define BLSP2_UART2_APPS_CLK_SRC 29
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#define GCC_AGGRE2_UFS_AXI_CLK 30
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#define GCC_AGGRE2_USB3_AXI_CLK 31
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#define GCC_BIMC_GFX_CLK 32
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#define GCC_BIMC_HMSS_AXI_CLK 33
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#define GCC_BIMC_MSS_Q6_AXI_CLK 34
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#define GCC_BLSP1_AHB_CLK 35
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43
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#define GCC_BLSP1_UART1_APPS_CLK 44
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#define GCC_BLSP1_UART2_APPS_CLK 45
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#define GCC_BLSP2_AHB_CLK 46
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54
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#define GCC_BLSP2_UART1_APPS_CLK 55
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#define GCC_BLSP2_UART2_APPS_CLK 56
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#define GCC_BOOT_ROM_AHB_CLK 57
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#define GCC_CFG_NOC_USB2_AXI_CLK 58
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#define GCC_CFG_NOC_USB3_AXI_CLK 59
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#define GCC_DCC_AHB_CLK 60
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#define GCC_GP1_CLK 61
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#define GCC_GP2_CLK 62
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#define GCC_GP3_CLK 63
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#define GCC_GPU_BIMC_GFX_CLK 64
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#define GCC_GPU_CFG_AHB_CLK 66
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#define GCC_GPU_GPLL0_CLK 67
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#define GCC_GPU_GPLL0_DIV_CLK 68
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#define GCC_HMSS_DVM_BUS_CLK 71
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#define GCC_HMSS_RBCPR_CLK 72
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#define GCC_MMSS_GPLL0_CLK 73
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#define GCC_MMSS_GPLL0_DIV_CLK 74
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#define GCC_MMSS_NOC_CFG_AHB_CLK 75
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#define GCC_MMSS_SYS_NOC_AXI_CLK 76
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#define GCC_MSS_CFG_AHB_CLK 77
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#define GCC_MSS_GPLL0_DIV_CLK 78
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#define GCC_MSS_MNOC_BIMC_AXI_CLK 79
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#define GCC_MSS_Q6_BIMC_AXI_CLK 80
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#define GCC_MSS_SNOC_AXI_CLK 81
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#define GCC_PDM2_CLK 82
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#define GCC_PDM_AHB_CLK 83
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#define GCC_PRNG_AHB_CLK 84
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#define GCC_QSPI_AHB_CLK 85
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#define GCC_QSPI_SER_CLK 86
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#define GCC_RX0_USB2_CLKREF_CLK 87
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#define GCC_RX1_USB2_CLKREF_CLK 88
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#define GCC_SDCC1_AHB_CLK 90
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#define GCC_SDCC1_APPS_CLK 91
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#define GCC_SDCC1_ICE_CORE_CLK 92
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#define GCC_SDCC2_AHB_CLK 93
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#define GCC_SDCC2_APPS_CLK 94
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#define GCC_UFS_AHB_CLK 95
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#define GCC_UFS_AXI_CLK 96
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#define GCC_UFS_CLKREF_CLK 97
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#define GCC_UFS_ICE_CORE_CLK 98
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#define GCC_UFS_PHY_AUX_CLK 99
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#define GCC_UFS_RX_SYMBOL_0_CLK 100
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#define GCC_UFS_RX_SYMBOL_1_CLK 101
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#define GCC_UFS_TX_SYMBOL_0_CLK 102
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#define GCC_UFS_UNIPRO_CORE_CLK 103
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#define GCC_USB20_MASTER_CLK 104
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#define GCC_USB20_MOCK_UTMI_CLK 105
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#define GCC_USB20_SLEEP_CLK 106
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#define GCC_USB30_MASTER_CLK 107
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#define GCC_USB30_MOCK_UTMI_CLK 108
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#define GCC_USB30_SLEEP_CLK 109
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#define GCC_USB3_CLKREF_CLK 110
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#define GCC_USB3_PHY_AUX_CLK 111
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#define GCC_USB3_PHY_PIPE_CLK 112
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113
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#define GP1_CLK_SRC 114
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#define GP2_CLK_SRC 115
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#define GP3_CLK_SRC 116
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#define GPLL0 117
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#define GPLL0_OUT_AUX 118
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#define GPLL0_OUT_AUX2 119
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#define GPLL0_OUT_EARLY 120
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#define GPLL0_OUT_MAIN 121
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#define GPLL0_AO 122
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#define GPLL1 123
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#define GPLL1_OUT_AUX 124
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#define GPLL1_OUT_AUX2 125
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#define GPLL1_OUT_EARLY 126
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#define GPLL1_OUT_MAIN 127
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#define GPLL1_OUT_TEST 128
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#define GPLL2 129
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#define GPLL2_OUT_AUX 130
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#define GPLL2_OUT_AUX2 131
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#define GPLL2_OUT_EARLY 132
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#define GPLL2_OUT_MAIN 133
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#define GPLL2_OUT_TEST 134
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#define GPLL3 135
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#define GPLL3_OUT_AUX 136
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#define GPLL3_OUT_AUX2 137
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#define GPLL3_OUT_EARLY 138
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#define GPLL3_OUT_MAIN 139
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#define GPLL3_OUT_TEST 140
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#define GPLL4 141
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#define GPLL4_OUT_AUX 142
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#define GPLL4_OUT_AUX2 143
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#define GPLL4_OUT_EARLY 144
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#define GPLL4_OUT_MAIN 145
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#define GPLL4_OUT_TEST 146
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#define GPLL5 147
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#define GPLL5_OUT_AUX 148
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#define GPLL5_OUT_AUX2 149
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#define GPLL5_OUT_EARLY 150
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#define GPLL5_OUT_MAIN 151
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#define GPLL5_OUT_TEST 152
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#define GPLL6 153
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#define GPLL6_OUT_AUX 154
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#define GPLL6_OUT_AUX2 155
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#define GPLL6_OUT_EARLY 156
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#define GPLL6_OUT_MAIN 157
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#define GPLL6_OUT_TEST 158
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#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159
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#define HMSS_GPLL0_CLK_SRC 161
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#define HMSS_GPLL4_CLK_SRC 162
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#define HMSS_RBCPR_CLK_SRC 163
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#define PDM2_CLK_SRC 164
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#define QSPI_SER_CLK_SRC 165
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#define SDCC1_APPS_CLK_SRC 166
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#define SDCC1_ICE_CORE_CLK_SRC 167
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#define SDCC2_APPS_CLK_SRC 168
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#define UFS_AXI_CLK_SRC 169
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#define UFS_ICE_CORE_CLK_SRC 170
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#define UFS_PHY_AUX_CLK_SRC 171
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#define UFS_UNIPRO_CORE_CLK_SRC 172
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#define USB20_MASTER_CLK_SRC 173
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#define USB20_MOCK_UTMI_CLK_SRC 174
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#define USB30_MASTER_CLK_SRC 175
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#define USB30_MOCK_UTMI_CLK_SRC 176
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#define USB3_PHY_AUX_CLK_SRC 177
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#define GPLL0_OUT_MSSCC 178
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#define GCC_UFS_AXI_HW_CTL_CLK 179
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#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180
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#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181
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#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182
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#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183
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#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184
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/* Block resets */
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#define GCC_QUSB2PHY_PRIM_BCR 0
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#define GCC_QUSB2PHY_SEC_BCR 1
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#define GCC_UFS_BCR 2
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#define GCC_USB3_DP_PHY_BCR 3
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#define GCC_USB3_PHY_BCR 4
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#define GCC_USB3PHY_PHY_BCR 5
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#define GCC_USB_20_BCR 6
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#define GCC_USB_30_BCR 7
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
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#endif
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