1242 lines
32 KiB
Devicetree
1242 lines
32 KiB
Devicetree
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/*
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* Copyright (c) 2018-2019, 2021 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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qcom,cam-req-mgr {
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compatible = "qcom,cam-req-mgr";
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status = "ok"
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};
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cam_csiphy0: qcom,csiphy@ace0000 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v1.2", "qcom,csiphy";
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reg = <0x0ace0000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0xe0000>;
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interrupts = <0 477 0>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen";
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gdscr-supply = <&titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-voltage = <1200000>;
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mipi-csi-vdd-supply = <&pm6150l_l3>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY0_CLK>,
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<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csi0phytimer_clk_src",
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"csi0phytimer_clk";
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src-clock-name = "csi0phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "turbo";
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clock-rates =
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<384000000 0 300000000 0>,
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<400000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy1: qcom,csiphy@ace2000{
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cell-index = <1>;
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compatible = "qcom,csiphy-v1.2", "qcom,csiphy";
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reg = <0xace2000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0xe2000>;
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interrupts = <0 478 0>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen";
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gdscr-supply = <&titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-voltage = <1200000>;
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mipi-csi-vdd-supply = <&pm6150l_l3>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY0_CLK>,
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<&clock_camcc CAM_CC_CSIPHY1_CLK>,
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<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csiphy1_clk",
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"csi1phytimer_clk_src",
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"csi1phytimer_clk";
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src-clock-name = "csi1phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "turbo";
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clock-rates =
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<384000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy2: qcom,csiphy@ace4000 {
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cell-index = <2>;
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compatible = "qcom,csiphy-v1.2", "qcom,csiphy";
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reg = <0xace4000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0xe4000>;
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interrupts = <0 479 0>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen";
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gdscr-supply = <&titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-voltage = <1200000>;
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mipi-csi-vdd-supply = <&pm6150l_l3>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY0_CLK>,
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<&clock_camcc CAM_CC_CSIPHY2_CLK>,
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<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csiphy2_clk",
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"csi2phytimer_clk_src",
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"csi2phytimer_clk";
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src-clock-name = "csi2phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "turbo";
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clock-rates =
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<384000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>;
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status = "ok"
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};
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cam_csiphy3: qcom,csiphy@ace6000 {
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cell-index = <3>;
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compatible = "qcom,csiphy-v1.2", "qcom,csiphy";
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reg = <0xace6000 0x2000>;
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reg-names = "csiphy";
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reg-cam-base = <0xe6000>;
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interrupts = <0 607 0>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen";
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gdscr-supply = <&titan_top_gdsc>;
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refgen-supply = <&refgen>;
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csi-vdd-voltage = <1200000>;
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mipi-csi-vdd-supply = <&pm6150l_l3>;
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clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&clock_camcc CAM_CC_CSIPHY0_CLK>,
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<&clock_camcc CAM_CC_CSIPHY3_CLK>,
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<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
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<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csiphy3_clk",
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"csi3phytimer_clk_src",
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"csi3phytimer_clk";
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src-clock-name = "csi3phytimer_clk_src";
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clock-cntl-level = "svs", "svs_l1", "turbo";
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clock-rates =
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<384000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>,
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<400000000 0 0 300000000 0>;
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status = "ok"
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};
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cam_cci0: qcom,cci@ac4a000 {
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cell-index = <0>;
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compatible = "qcom,cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xac4a000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x4a000>;
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interrupt-names = "cci";
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interrupts = <0 460 0>;
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status = "ok"
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gdscr-supply = <&titan_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&clock_camcc CAM_CC_CCI_0_CLK>,
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<&clock_camcc CAM_CC_CCI_0_CLK_SRC>;
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clock-names = "cci_0_clk",
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"cci_0_clk_src";
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src-clock-name = "cci_0_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci0_active &cci1_active>;
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pinctrl-1 = <&cci0_suspend &cci1_suspend>;
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gpios = <&tlmm 17 0>,
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<&tlmm 18 0>,
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<&tlmm 19 0>,
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<&tlmm 20 0>;
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gpio-req-tbl-num = <0 1 2 3>;
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gpio-req-tbl-flags = <1 1 1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA0",
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"CCI_I2C_CLK0",
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"CCI_I2C_DATA1",
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"CCI_I2C_CLK1";
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i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_custom_cci0: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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};
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cam_cci1: qcom,cci@ac4b000 {
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cell-index = <1>;
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compatible = "qcom,cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xac4b000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x4b000>;
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interrupt-names = "cci";
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interrupts = <0 461 0>;
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status = "ok"
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gdscr-supply = <&titan_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&clock_camcc CAM_CC_CCI_1_CLK>,
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<&clock_camcc CAM_CC_CCI_1_CLK_SRC>;
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clock-names = "cci_clk",
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"cci_1_clk_src";
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src-clock-name = "cci_1_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci2_active>;
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pinctrl-1 = <&cci2_suspend>;
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gpios = <&tlmm 27 0>,
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<&tlmm 28 0>;
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gpio-req-tbl-num = <0 1>;
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gpio-req-tbl-flags = <1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA2",
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"CCI_I2C_CLK2";
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i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_custom_cci1: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok"
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};
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i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
|
||
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hw-tlow = <22>;
|
||
|
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hw-tsu-sto = <17>;
|
||
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hw-tsu-sta = <18>;
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||
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hw-thd-dat = <16>;
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||
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hw-thd-sta = <15>;
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||
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hw-tbuf = <24>;
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||
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hw-scl-stretch-en = <0>;
|
||
|
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hw-trdhld = <3>;
|
||
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hw-tsp = <3>;
|
||
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cci-clk-src = <37500000>;
|
||
|
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status = "ok"
|
||
|
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};
|
||
|
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};
|
||
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|
||
|
|
qcom,cam_smmu {
|
||
|
|
compatible = "qcom,msm-cam-smmu";
|
||
|
|
status = "ok"
|
||
|
|
|
||
|
|
msm_cam_smmu_ife {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x900 0x460>,
|
||
|
|
<&apps_smmu 0xD00 0x460>,
|
||
|
|
<&apps_smmu 0x880 0x460>,
|
||
|
|
<&apps_smmu 0xC80 0x460>,
|
||
|
|
<&apps_smmu 0x820 0x440>,
|
||
|
|
<&apps_smmu 0xC20 0x440>,
|
||
|
|
<&apps_smmu 0x920 0x460>,
|
||
|
|
<&apps_smmu 0xD20 0x460>,
|
||
|
|
<&apps_smmu 0x8A0 0x460>,
|
||
|
|
<&apps_smmu 0xCA0 0x460>,
|
||
|
|
<&apps_smmu 0x940 0x460>,
|
||
|
|
<&apps_smmu 0xD40 0x460>,
|
||
|
|
<&apps_smmu 0x8C0 0x460>,
|
||
|
|
<&apps_smmu 0xCC0 0x460>;
|
||
|
|
label = "ife";
|
||
|
|
ife_iova_mem_map: iova-mem-map {
|
||
|
|
/* IO region is approximately 3.4 GB */
|
||
|
|
iova-mem-region-io {
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0xd8c00000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_jpeg {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x1280 0x20>,
|
||
|
|
<&apps_smmu 0x12A0 0x20>;
|
||
|
|
label = "jpeg";
|
||
|
|
jpeg_iova_mem_map: iova-mem-map {
|
||
|
|
/* IO region is approximately 3.4 GB */
|
||
|
|
iova-mem-region-io {
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0xd8c00000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_icp_fw {
|
||
|
|
compatible = "qcom,msm-cam-smmu-fw-dev";
|
||
|
|
label="icp";
|
||
|
|
memory-region = <&pil_camera_mem>;
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_icp {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x1180 0x0>,
|
||
|
|
<&apps_smmu 0x11E0 0x0>,
|
||
|
|
<&apps_smmu 0x11A0 0x0>,
|
||
|
|
<&apps_smmu 0x1200 0x0>,
|
||
|
|
<&apps_smmu 0x1260 0x0>,
|
||
|
|
<&apps_smmu 0x1220 0x0>,
|
||
|
|
<&apps_smmu 0x1042 0x0>,
|
||
|
|
<&apps_smmu 0x1300 0x60>,
|
||
|
|
<&apps_smmu 0x1320 0x60>;
|
||
|
|
label = "icp";
|
||
|
|
icp_iova_mem_map: iova-mem-map {
|
||
|
|
iova-mem-region-firmware {
|
||
|
|
/* Firmware region is 5MB */
|
||
|
|
iova-region-name = "firmware";
|
||
|
|
iova-region-start = <0x0>;
|
||
|
|
iova-region-len = <0x500000>;
|
||
|
|
iova-region-id = <0x0>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
iova-mem-region-shared {
|
||
|
|
/* Shared region is 150MB long */
|
||
|
|
iova-region-name = "shared";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0x9600000>;
|
||
|
|
iova-region-id = <0x1>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
iova-mem-region-secondary-heap {
|
||
|
|
/* Secondary heap region is 1MB long */
|
||
|
|
iova-region-name = "secheap";
|
||
|
|
iova-region-start = <0x10A00000>;
|
||
|
|
iova-region-len = <0x100000>;
|
||
|
|
iova-region-id = <0x4>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
iova-mem-region-io {
|
||
|
|
/* IO region is approximately 3 GB */
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0x10C00000>;
|
||
|
|
iova-region-len = <0xA9C00000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
iova-mem-qdss-region {
|
||
|
|
/* QDSS region is appropriate 1MB */
|
||
|
|
iova-region-name = "qdss";
|
||
|
|
iova-region-start = <0x10B00000>;
|
||
|
|
iova-region-len = <0x100000>;
|
||
|
|
iova-region-id = <0x5>;
|
||
|
|
qdss-phy-addr = <0x16790000>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_cpas_cdm {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x1000 0x0>;
|
||
|
|
label = "cpas-cdm0";
|
||
|
|
cpas_cdm_iova_mem_map: iova-mem-map {
|
||
|
|
iova-mem-region-io {
|
||
|
|
/* IO region is approximately 3.4 GB */
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0xd8c00000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_secure {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
label = "cam-secure";
|
||
|
|
qcom,secure-cb;
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_fd {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x12C0 0x20>,
|
||
|
|
<&apps_smmu 0x12E0 0x20>;
|
||
|
|
label = "fd";
|
||
|
|
fd_iova_mem_map: iova-mem-map {
|
||
|
|
iova-mem-region-io {
|
||
|
|
/* IO region is approximately 3.4 GB */
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0xd8c00000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msm_cam_smmu_lrme {
|
||
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
||
|
|
iommus = <&apps_smmu 0x11C0 0x0>,
|
||
|
|
<&apps_smmu 0x1240 0x0>;
|
||
|
|
label = "lrme";
|
||
|
|
lrme_iova_mem_map: iova-mem-map {
|
||
|
|
iova-mem-region-shared {
|
||
|
|
/* Shared region is 100MB long */
|
||
|
|
iova-region-name = "shared";
|
||
|
|
iova-region-start = <0x7400000>;
|
||
|
|
iova-region-len = <0x6400000>;
|
||
|
|
iova-region-id = <0x1>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
/* IO region is approximately 3.3 GB */
|
||
|
|
iova-mem-region-io {
|
||
|
|
iova-region-name = "io";
|
||
|
|
iova-region-start = <0xd800000>;
|
||
|
|
iova-region-len = <0xd2800000>;
|
||
|
|
iova-region-id = <0x3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-cdm-intf {
|
||
|
|
compatible = "qcom,cam-cdm-intf";
|
||
|
|
cell-index = <0>;
|
||
|
|
label = "cam-cdm-intf";
|
||
|
|
num-hw-cdm = <1>;
|
||
|
|
cdm-client-names = "vfe",
|
||
|
|
"jpegdma",
|
||
|
|
"jpegenc",
|
||
|
|
"fd",
|
||
|
|
"lrmecdm";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cpas-cdm0@ac48000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam170-cpas-cdm0";
|
||
|
|
label = "cpas-cdm";
|
||
|
|
reg = <0xac48000 0x1000>;
|
||
|
|
reg-names = "cpas-cdm";
|
||
|
|
reg-cam-base = <0x48000>;
|
||
|
|
interrupts = <0 468 0>;
|
||
|
|
interrupt-names = "cpas-cdm";
|
||
|
|
regulator-names = "camss";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names = "cam_cc_cpas_slow_ahb_clk",
|
||
|
|
"cam_cc_cpas_ahb_clk";
|
||
|
|
clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_CPAS_AHB_CLK>;
|
||
|
|
clock-rates = <0 0>;
|
||
|
|
clock-cntl-level = "svs";
|
||
|
|
cdm-client-names = "ife";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-isp {
|
||
|
|
compatible = "qcom,cam-isp";
|
||
|
|
arch-compat = "ife";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_csid0: qcom,csid0@acb3000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,csid175_200";
|
||
|
|
reg-names = "csid";
|
||
|
|
reg = <0xacb3000 0x1000>;
|
||
|
|
reg-cam-base = <0xb3000>;
|
||
|
|
interrupt-names = "csid";
|
||
|
|
interrupts = <0 464 0>;
|
||
|
|
regulator-names = "camss", "ife0";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
ife0-supply = <&ife_0_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_csid_clk_src",
|
||
|
|
"ife_csid_clk",
|
||
|
|
"cphy_rx_clk_src",
|
||
|
|
"ife_cphy_rx_clk",
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk",
|
||
|
|
"ife_axi_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<300000000 0 0 0 380000000 0 0>,
|
||
|
|
<384000000 0 0 0 510000000 0 0>,
|
||
|
|
<400000000 0 0 0 637000000 0 0>,
|
||
|
|
<400000000 0 0 0 760000000 0 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_csid_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_vfe0: qcom,vfe0@acaf000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,vfe175_130";
|
||
|
|
reg-names = "ife";
|
||
|
|
reg = <0xacaf000 0x5200>;
|
||
|
|
reg-cam-base = <0xaf000>;
|
||
|
|
interrupt-names = "ife";
|
||
|
|
interrupts = <0 465 0>;
|
||
|
|
regulator-names = "camss", "ife0";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
ife0-supply = <&ife_0_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk",
|
||
|
|
"ife_axi_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<380000000 0 0>,
|
||
|
|
<510000000 0 0>,
|
||
|
|
<637000000 0 0>,
|
||
|
|
<760000000 0 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clock-names-option = "ife_dsp_clk";
|
||
|
|
clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;
|
||
|
|
clock-rates-option = <760000000>;
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_csid1: qcom,csid1@acba000 {
|
||
|
|
cell-index = <1>;
|
||
|
|
compatible = "qcom,csid175_200";
|
||
|
|
reg-names = "csid";
|
||
|
|
reg = <0xacba000 0x1000>;
|
||
|
|
reg-cam-base = <0xba000>;
|
||
|
|
interrupt-names = "csid";
|
||
|
|
interrupts = <0 466 0>;
|
||
|
|
regulator-names = "camss", "ife1";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
ife1-supply = <&ife_1_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_csid_clk_src",
|
||
|
|
"ife_csid_clk",
|
||
|
|
"cphy_rx_clk_src",
|
||
|
|
"ife_cphy_rx_clk",
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk",
|
||
|
|
"ife_axi_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<300000000 0 0 0 380000000 0 0>,
|
||
|
|
<384000000 0 0 0 510000000 0 0>,
|
||
|
|
<400000000 0 0 0 637000000 0 0>,
|
||
|
|
<400000000 0 0 0 760000000 0 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_csid_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_vfe1: qcom,vfe1@acb6000 {
|
||
|
|
cell-index = <1>;
|
||
|
|
compatible = "qcom,vfe175_130";
|
||
|
|
reg-names = "ife";
|
||
|
|
reg = <0xacb6000 0x5200>;
|
||
|
|
reg-cam-base = <0xb6000>;
|
||
|
|
interrupt-names = "ife";
|
||
|
|
interrupts = <0 467 0>;
|
||
|
|
regulator-names = "camss", "ife1";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
ife1-supply = <&ife_1_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk",
|
||
|
|
"ife_axi_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<380000000 0 0>,
|
||
|
|
<510000000 0 0>,
|
||
|
|
<637000000 0 0>,
|
||
|
|
<760000000 0 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clock-names-option = "ife_dsp_clk";
|
||
|
|
clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;
|
||
|
|
clock-rates-option = <760000000>;
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_csid_lite0: qcom,csid-lite0@acc8000 {
|
||
|
|
cell-index = <2>;
|
||
|
|
compatible = "qcom,csid-lite175";
|
||
|
|
reg-names = "csid-lite";
|
||
|
|
reg = <0xacc8000 0x1000>;
|
||
|
|
reg-cam-base = <0xc8000>;
|
||
|
|
interrupt-names = "csid-lite";
|
||
|
|
interrupts = <0 438 0>;
|
||
|
|
regulator-names = "camss";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_csid_clk_src",
|
||
|
|
"ife_csid_clk",
|
||
|
|
"cphy_rx_clk_src",
|
||
|
|
"ife_cphy_rx_clk",
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<300000000 0 0 0 320000000 0>,
|
||
|
|
<384000000 0 0 0 400000000 0>,
|
||
|
|
<400000000 0 0 0 480000000 0>,
|
||
|
|
<400000000 0 0 0 600000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_csid_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_vfe_lite0: qcom,vfe-lite0@acc4000 {
|
||
|
|
cell-index = <2>;
|
||
|
|
compatible = "qcom,vfe-lite175";
|
||
|
|
reg-names = "ife-lite";
|
||
|
|
reg = <0xacc4000 0x4000>;
|
||
|
|
reg-cam-base = <0xc4000>;
|
||
|
|
interrupt-names = "ife-lite";
|
||
|
|
interrupts = <0 434 0>;
|
||
|
|
regulator-names = "camss";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ife_clk_src",
|
||
|
|
"ife_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IFE_LITE_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<320000000 0>,
|
||
|
|
<400000000 0>,
|
||
|
|
<480000000 0>,
|
||
|
|
<600000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "ife_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-icp {
|
||
|
|
compatible = "qcom,cam-icp";
|
||
|
|
compat-hw-name = "qcom,a5",
|
||
|
|
"qcom,ipe0",
|
||
|
|
"qcom,ipe1",
|
||
|
|
"qcom,bps";
|
||
|
|
num-a5 = <1>;
|
||
|
|
num-ipe = <2>;
|
||
|
|
num-bps = <1>;
|
||
|
|
icp_pc_en;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_a5: qcom,a5@ac00000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam-a5";
|
||
|
|
reg = <0xac00000 0x6000>,
|
||
|
|
<0xac10000 0x8000>,
|
||
|
|
<0xac18000 0x3000>;
|
||
|
|
reg-names = "a5_qgic", "a5_sierra", "a5_csr";
|
||
|
|
reg-cam-base = <0x00000 0x10000 0x18000>;
|
||
|
|
interrupts = <0 463 0>;
|
||
|
|
interrupt-names = "a5";
|
||
|
|
regulator-names = "camss-vdd";
|
||
|
|
camss-vdd-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"soc_fast_ahb",
|
||
|
|
"icp_ahb_clk",
|
||
|
|
"icp_clk_src",
|
||
|
|
"icp_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_ICP_AHB_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_ICP_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_ICP_CLK>;
|
||
|
|
|
||
|
|
clock-rates =
|
||
|
|
<200000000 0 400000000 0>,
|
||
|
|
<400000000 0 600000000 0>;
|
||
|
|
clock-cntl-level = "svs", "turbo";
|
||
|
|
fw_name = "CAMERA_ICP.elf";
|
||
|
|
ubwc-cfg = <0x73 0x1CF>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_ipe0: qcom,ipe0 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam-ipe";
|
||
|
|
reg = <0xac87000 0x3000>;
|
||
|
|
reg-names = "ipe0_top";
|
||
|
|
reg-cam-base = <0x87000>;
|
||
|
|
regulator-names = "ipe0-vdd";
|
||
|
|
ipe0-vdd-supply = <&ipe_0_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ipe_0_ahb_clk",
|
||
|
|
"ipe_0_areg_clk",
|
||
|
|
"ipe_0_axi_clk",
|
||
|
|
"ipe_0_clk_src",
|
||
|
|
"ipe_0_clk";
|
||
|
|
src-clock-name = "ipe_0_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_CLK>;
|
||
|
|
|
||
|
|
clock-rates =
|
||
|
|
<0 0 0 340000000 0>,
|
||
|
|
<0 0 0 430000000 0>,
|
||
|
|
<0 0 0 520000000 0>,
|
||
|
|
<0 0 0 600000000 0>,
|
||
|
|
<0 0 0 600000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1",
|
||
|
|
"nominal", "turbo";
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_ipe1: qcom,ipe1 {
|
||
|
|
cell-index = <1>;
|
||
|
|
compatible = "qcom,cam-ipe";
|
||
|
|
reg = <0xac91000 0x3000>;
|
||
|
|
reg-names = "ipe1_top";
|
||
|
|
reg-cam-base = <0x91000>;
|
||
|
|
regulator-names = "ipe1-vdd";
|
||
|
|
ipe1-vdd-supply = <&ipe_1_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"ipe_1_ahb_clk",
|
||
|
|
"ipe_1_areg_clk",
|
||
|
|
"ipe_1_axi_clk",
|
||
|
|
"ipe_1_clk_src",
|
||
|
|
"ipe_1_clk";
|
||
|
|
src-clock-name = "ipe_1_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_IPE_1_AHB_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_IPE_1_CLK>;
|
||
|
|
|
||
|
|
clock-rates =
|
||
|
|
<0 0 0 340000000 0>,
|
||
|
|
<0 0 0 430000000 0>,
|
||
|
|
<0 0 0 520000000 0>,
|
||
|
|
<0 0 0 600000000 0>,
|
||
|
|
<0 0 0 600000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1",
|
||
|
|
"nominal", "turbo";
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_bps: qcom,bps {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam-bps";
|
||
|
|
reg = <0xac6f000 0x3000>;
|
||
|
|
reg-names = "bps_top";
|
||
|
|
reg-cam-base = <0x6f000>;
|
||
|
|
regulator-names = "bps-vdd";
|
||
|
|
bps-vdd-supply = <&bps_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"bps_ahb_clk",
|
||
|
|
"bps_areg_clk",
|
||
|
|
"bps_axi_clk",
|
||
|
|
"bps_clk_src",
|
||
|
|
"bps_clk";
|
||
|
|
src-clock-name = "bps_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_BPS_AHB_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_BPS_AREG_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_BPS_AXI_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_BPS_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_BPS_CLK>;
|
||
|
|
|
||
|
|
clock-rates =
|
||
|
|
<0 0 0 200000000 0>,
|
||
|
|
<0 0 0 400000000 0>,
|
||
|
|
<0 0 0 480000000 0>,
|
||
|
|
<0 0 0 600000000 0>,
|
||
|
|
<0 0 0 600000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1",
|
||
|
|
"nominal", "turbo";
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-jpeg {
|
||
|
|
compatible = "qcom,cam-jpeg";
|
||
|
|
compat-hw-name = "qcom,jpegenc",
|
||
|
|
"qcom,jpegdma";
|
||
|
|
num-jpeg-enc = <1>;
|
||
|
|
num-jpeg-dma = <1>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_jpeg_enc: qcom,jpegenc@ac4e000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam_jpeg_enc";
|
||
|
|
reg-names = "jpege_hw";
|
||
|
|
reg = <0xac4e000 0x4000>;
|
||
|
|
reg-cam-base = <0x4e000>;
|
||
|
|
interrupt-names = "jpeg";
|
||
|
|
interrupts = <0 474 0>;
|
||
|
|
regulator-names = "camss-vdd";
|
||
|
|
camss-vdd-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"jpegenc_clk_src",
|
||
|
|
"jpegenc_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_JPEG_CLK>;
|
||
|
|
|
||
|
|
clock-rates = <600000000 0>;
|
||
|
|
src-clock-name = "jpegenc_clk_src";
|
||
|
|
clock-cntl-level = "nominal";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_jpeg_dma: qcom,jpegdma@ac52000{
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam_jpeg_dma";
|
||
|
|
reg-names = "jpegdma_hw";
|
||
|
|
reg = <0xac52000 0x4000>;
|
||
|
|
reg-cam-base = <0x52000>;
|
||
|
|
interrupt-names = "jpegdma";
|
||
|
|
interrupts = <0 475 0>;
|
||
|
|
regulator-names = "camss-vdd";
|
||
|
|
camss-vdd-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"jpegdma_clk_src",
|
||
|
|
"jpegdma_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_JPEG_CLK>;
|
||
|
|
|
||
|
|
clock-rates = <600000000 0>;
|
||
|
|
src-clock-name = "jpegdma_clk_src";
|
||
|
|
clock-cntl-level = "nominal";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-fd {
|
||
|
|
compatible = "qcom,cam-fd";
|
||
|
|
compat-hw-name = "qcom,fd";
|
||
|
|
num-fd = <1>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_fd: qcom,fd@ac5a000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,fd501";
|
||
|
|
reg-names = "fd_core", "fd_wrapper";
|
||
|
|
reg = <0xac5a000 0x1000>,
|
||
|
|
<0xac5b000 0x400>;
|
||
|
|
reg-cam-base = <0x5a000 0x5b000>;
|
||
|
|
interrupt-names = "fd";
|
||
|
|
interrupts = <0 462 0>;
|
||
|
|
regulator-names = "camss-vdd";
|
||
|
|
camss-vdd-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"fd_core_clk_src",
|
||
|
|
"fd_core_clk",
|
||
|
|
"fd_core_uar_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_FD_CORE_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_FD_CORE_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;
|
||
|
|
src-clock-name = "fd_core_clk_src";
|
||
|
|
clock-control-debugfs = "true";
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
clock-rates =
|
||
|
|
<380000000 0 0>,
|
||
|
|
<400000000 0 0>,
|
||
|
|
<480000000 0 0>,
|
||
|
|
<600000000 0 0>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-lrme {
|
||
|
|
compatible = "qcom,cam-lrme";
|
||
|
|
arch-compat = "lrme";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
cam_lrme: qcom,lrme@ac6b000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,lrme";
|
||
|
|
reg-names = "lrme";
|
||
|
|
reg = <0xac6b000 0xa00>;
|
||
|
|
reg-cam-base = <0x6b000>;
|
||
|
|
interrupt-names = "lrme";
|
||
|
|
interrupts = <0 476 0>;
|
||
|
|
regulator-names = "camss";
|
||
|
|
camss-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"lrme_clk_src",
|
||
|
|
"lrme_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_camcc CAM_CC_LRME_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_LRME_CLK>;
|
||
|
|
clock-rates =
|
||
|
|
<240000000 0>,
|
||
|
|
<300000000 0>,
|
||
|
|
<320000000 0>,
|
||
|
|
<400000000 0>;
|
||
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
||
|
|
src-clock-name = "lrme_clk_src";
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,cam-cpas@ac40000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,cam-cpas";
|
||
|
|
label = "cpas";
|
||
|
|
arch-compat = "cpas_top";
|
||
|
|
status = "ok"
|
||
|
|
reg-names = "cam_cpas_top", "cam_camnoc";
|
||
|
|
reg = <0xac40000 0x1000>,
|
||
|
|
<0xac42000 0x6000>;
|
||
|
|
reg-cam-base = <0x40000 0x42000>;
|
||
|
|
interrupt-names = "cpas_camnoc";
|
||
|
|
interrupts = <0 459 0>;
|
||
|
|
camnoc-axi-min-ib-bw = <3000000000>;
|
||
|
|
regulator-names = "camss-vdd";
|
||
|
|
camss-vdd-supply = <&titan_top_gdsc>;
|
||
|
|
clock-names =
|
||
|
|
"gcc_ahb_clk",
|
||
|
|
"gcc_axi_hf_clk",
|
||
|
|
"gcc_axi_sf_clk",
|
||
|
|
"slow_ahb_clk_src",
|
||
|
|
"cpas_ahb_clk",
|
||
|
|
"camnoc_axi_clk_src",
|
||
|
|
"camnoc_axi_clk";
|
||
|
|
clocks =
|
||
|
|
<&clock_gcc GCC_CAMERA_AHB_CLK>,
|
||
|
|
<&clock_gcc GCC_CAMERA_HF_AXI_CLK>,
|
||
|
|
<&clock_gcc GCC_CAMERA_SF_AXI_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
|
||
|
|
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
|
||
|
|
<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
|
||
|
|
src-clock-name = "camnoc_axi_clk_src";
|
||
|
|
clock-rates =
|
||
|
|
<0 0 0 0 0 0 0>,
|
||
|
|
<0 0 0 80000000 0 150000000 0>,
|
||
|
|
<0 0 0 80000000 0 240000000 0>,
|
||
|
|
<0 0 0 80000000 0 320000000 0>,
|
||
|
|
<0 0 0 80000000 0 400000000 0>,
|
||
|
|
<0 0 0 80000000 0 480000000 0>;
|
||
|
|
clock-cntl-level = "suspend", "lowsvs", "svs",
|
||
|
|
"svs_l1", "nominal", "turbo";
|
||
|
|
qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
|
||
|
|
control-camnoc-axi-clk;
|
||
|
|
camnoc-bus-width = <32>;
|
||
|
|
camnoc-axi-clk-bw-margin-perc = <20>;
|
||
|
|
qcom,msm-bus,name = "cam_ahb";
|
||
|
|
qcom,msm-bus,num-cases = <6>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 120000>,
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
|
||
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
||
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
|
||
|
|
vdd-corners = <RPMH_REGULATOR_LEVEL_OFF
|
||
|
|
RPMH_REGULATOR_LEVEL_RETENTION
|
||
|
|
RPMH_REGULATOR_LEVEL_MIN_SVS
|
||
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS
|
||
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM_L1
|
||
|
|
RPMH_REGULATOR_LEVEL_NOM_L2
|
||
|
|
RPMH_REGULATOR_LEVEL_TURBO
|
||
|
|
RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||
|
|
vdd-corner-ahb-mapping = "suspend", "suspend",
|
||
|
|
"minsvs", "lowsvs", "svs", "svs_l1",
|
||
|
|
"nominal", "nominal", "nominal",
|
||
|
|
"turbo", "turbo";
|
||
|
|
client-id-based;
|
||
|
|
client-names =
|
||
|
|
"csiphy0", "csiphy1", "csiphy2", "csiphy3",
|
||
|
|
"cci0", "cci1",
|
||
|
|
"csid0", "csid1", "csid2",
|
||
|
|
"iferdi0", "ifenrdi0", "iferdi1", "ifenrdi1",
|
||
|
|
"iferdi2", "ifenrdi2",
|
||
|
|
"ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0",
|
||
|
|
"bps0", "icp0", "jpeg-dma0", "jpeg-enc0",
|
||
|
|
"fd0", "lrmecpas0";
|
||
|
|
client-axi-port-names =
|
||
|
|
"cam_hf_0", "cam_hf_0", "cam_hf_0", "cam_hf_0",
|
||
|
|
"cam_sf_0", "cam_sf_0",
|
||
|
|
"cam_hf_0", "cam_hf_0", "cam_hf_0",
|
||
|
|
"cam_hf_1", "cam_hf_0", "cam_hf_1", "cam_hf_0",
|
||
|
|
"cam_hf_1", "cam_hf_0",
|
||
|
|
"cam_sf_0", "cam_sf_0", "cam_sf_0", "cam_sf_0",
|
||
|
|
"cam_sf_0", "cam_sf_1", "cam_sf_0", "cam_sf_0",
|
||
|
|
"cam_sf_0", "cam_sf_0";
|
||
|
|
client-bus-camnoc-based;
|
||
|
|
qcom,axi-port-list {
|
||
|
|
qcom,axi-port1 {
|
||
|
|
/* this port is clubbed port of two ports
|
||
|
|
* (READ and PIX ports)
|
||
|
|
*/
|
||
|
|
qcom,axi-port-name = "cam_hf_0";
|
||
|
|
ib-bw-voting-needed;
|
||
|
|
qcom,axi-port-mnoc {
|
||
|
|
qcom,msm-bus,name = "cam_hf_0_mnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_HF0
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_HF0
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
||
|
|
};
|
||
|
|
qcom,axi-port-camnoc {
|
||
|
|
qcom,msm-bus,name = "cam_hf_0_camnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
qcom,axi-port2 {
|
||
|
|
/* this port is for rdi only WR*/
|
||
|
|
qcom,axi-port-name = "cam_hf_1";
|
||
|
|
ib-bw-voting-needed;
|
||
|
|
qcom,axi-port-mnoc {
|
||
|
|
qcom,msm-bus,name = "cam_hf_1_mnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_RT
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_RT
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
||
|
|
};
|
||
|
|
qcom,axi-port-camnoc {
|
||
|
|
qcom,msm-bus,name = "cam_hf_1_camnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_RT_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_RT_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
qcom,axi-port3 {
|
||
|
|
qcom,axi-port-name = "cam_sf_0";
|
||
|
|
qcom,axi-port-mnoc {
|
||
|
|
qcom,msm-bus,name = "cam_sf_0_mnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_SF
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_SF
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
||
|
|
};
|
||
|
|
qcom,axi-port-camnoc {
|
||
|
|
qcom,msm-bus,name = "cam_sf_0_camnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
qcom,axi-port4 {
|
||
|
|
qcom,axi-port-name = "cam_sf_1";
|
||
|
|
qcom,axi-port-mnoc {
|
||
|
|
qcom,msm-bus,name = "cam_sf_1_mnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_NRT
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_NRT
|
||
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
||
|
|
};
|
||
|
|
qcom,axi-port-camnoc {
|
||
|
|
qcom,msm-bus,name = "cam_sf_1_camnoc";
|
||
|
|
qcom,msm-bus-vector-dyn-vote;
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_NRT_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
||
|
|
<MSM_BUS_MASTER_CAMNOC_NRT_UNCOMP
|
||
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|