218 lines
6.1 KiB
Devicetree
218 lines
6.1 KiB
Devicetree
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/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x140 0x0>;
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qcom,smmu-s1-bypass;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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clocks = <&clock_virt GCC_USB30_PRIM_MASTER_CLK>,
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<&clock_virt GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&clock_virt GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&clock_virt GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&clock_virt GCC_USB30_PRIM_SLEEP_CLK>,
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<&clock_virt GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&clock_virt GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
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qcom,ignore-wakeup-src-in-hostmode;
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status = "disabled";
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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interrupts = <0 133 0>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,ssp-u3-u0-quirk;
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snps,usb3-u1u2-disable;
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usb-core-id = <0>;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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usbbam: qcom,usbbam@a704000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0xa704000 0x17000>;
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interrupts = <0 132 0>;
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qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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status = "disabled";
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x6064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e2000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e2000 0x110>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&pm8195_3_l5>;
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vdda18-supply = <&pm8195_1_l12>;
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vdda33-supply = <&pm8195_3_l16>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&clock_gcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&clock_virt GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq = <0x43 0x70>;
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status = "disabled";
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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/* Secondary USB port related controller */
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usb1: ssusb@a800000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a800000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x160 0x0>;
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qcom,smmu-s1-bypass;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb30_sec_gdsc>;
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clocks = <&clock_virt GCC_USB30_SEC_MASTER_CLK>,
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<&clock_virt GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&clock_virt GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&clock_virt GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&clock_virt GCC_USB30_SEC_SLEEP_CLK>,
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<&clock_virt GCC_USB3_SEC_CLKREF_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&clock_virt GCC_USB30_SEC_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
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qcom,charging-disabled;
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status = "disabled";
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dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0x0a800000 0xcd00>;
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interrupts = <0 138 0>;
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usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <1>;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Secondary USB port related High Speed PHY */
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usb2_phy1: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e3000 0x110>;
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reg-names = "hsusb_phy_base";
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vdd-supply = <&pm8195_3_l5>;
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vdda18-supply = <&pm8195_1_l12>;
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vdda33-supply = <&pm8195_3_l16>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&clock_gcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&clock_virt GCC_QUSB2PHY_SEC_BCR>;
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reset-names = "phy_reset";
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status = "disabled";
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};
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};
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