578 lines
15 KiB
Devicetree
578 lines
15 KiB
Devicetree
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/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,tcs-mbox.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDMSHRIKE";
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compatible = "qcom,sdmshrike";
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qcom,msm-name = "SDMSHRIKE";
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qcom,msm-id = <340 0x10000>;
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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#cooling-cells = <0x2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_2>;
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#cooling-cells = <2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_3>;
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#cooling-cells = <2>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_4>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_5>;
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#cooling-cells = <2>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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#cooling-cells = <2>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_7>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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};
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soc: soc { } ;
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chosen {
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bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
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};
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aliases {
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serial0 = &qupv3_se12_2uart;
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serial1 = "/soc/qcom,qup_uart@0xa90000";
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};
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memory {
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device_type = "memory";
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reg = <0x1 0x40000000 0x0 0x20000000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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#include "sdmshrike-gdsc.dtsi"
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&soc {
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status = "ok"
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0x0 0x0 0x0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <1 9 4>;
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interrupt-parent = <&intc>;
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};
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clock_gcc: qcom,gcc@100000 {
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compatible = "qcom,gcc-sdmshrike", "syscon";
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reg = <0x100000 0x1f0000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
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vdd_mm-supply = <&VDD_MMCX_LEVEL>;
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#clock-cells = <0x1>;
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#reset-cells = <0x1>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 1 0xf08>,
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<1 2 0xf08>,
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<1 3 0xf08>,
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<1 0 0xf08>;
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clock-frequency = <19200000>;
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};
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timer@0x17c20000 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@0x17c21000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <0 0 0>, <0 1 0>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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qcom,msm-imem@146bf000 {
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compatible = "qcom,msm-imem";
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reg = <0x146bf000 0x1000>;
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ranges = <0x0 0x146bf000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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};
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restart@c264000 {
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compatible = "qcom,pshold";
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reg = <0xc264000 0x4>,
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<0x1fd3000 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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apps_rsc: mailbox@18220000 {
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compatible = "qcom,tcs-drv";
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status="ok"
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label = "apps_rsc";
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reg = <0x18220000 0x100>, <0x18220d00 0x3000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>;
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};
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clock_rpmh: qcom,rpmhclk {
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compatible = "qcom,rpmh-clk-sdmshrike";
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mboxes = <&apps_rsc 0>;
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mbox-names = "apps";
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#clock-cells = <1>;
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};
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disp_rsc: mailbox@af20000 {
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compatible = "qcom,tcs-drv";
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label = "display_rsc";
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reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
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interrupts = <0 129 0>;
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#mbox-cells = <1>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<ACTIVE_TCS 2>,
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<CONTROL_TCS 0>;
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status = "disabled";
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};
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qmp_aop: qcom,qmp-aop@c300000 {
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compatible = "qcom,qmp-mbox";
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reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
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reg-names = "msgram", "irq-reg-base";
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qcom,irq-mask = <0x1>;
|
||
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
||
|
|
|
||
|
|
label = "aop";
|
||
|
|
qcom,early-boot;
|
||
|
|
priority = <0>;
|
||
|
|
mbox-desc-offset = <0x0>;
|
||
|
|
#mbox-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd_db: qcom,cmd-db@c3f000c {
|
||
|
|
compatible = "qcom,cmd-db";
|
||
|
|
reg = <0xc3f000c 8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||
|
|
compatible = "qcom,qupv3-geni-se";
|
||
|
|
reg = <0xac0000 0x6000>;
|
||
|
|
qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
|
||
|
|
qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
|
||
|
|
qcom,iommu-s1-bypass;
|
||
|
|
|
||
|
|
iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
|
||
|
|
compatible = "qcom,qupv3-geni-se-cb";
|
||
|
|
iommus = <&apps_smmu 0x603 0x0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
/* 2-wire UART */
|
||
|
|
|
||
|
|
/* Debug UART Instance for CDP/MTP platform */
|
||
|
|
qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
|
||
|
|
compatible = "qcom,msm-geni-console";
|
||
|
|
reg = <0xa90000 0x4000>;
|
||
|
|
reg-names = "se_phys";
|
||
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||
|
|
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
||
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||
|
|
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <&qupv3_se12_2uart_active>;
|
||
|
|
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
|
||
|
|
interrupts = <GIC_SPI 357 0>;
|
||
|
|
qcom,wrapper-core = <&qupv3_1>;
|
||
|
|
status = "ok"
|
||
|
|
};
|
||
|
|
|
||
|
|
apps_smmu: apps-smmu@0x15000000 {
|
||
|
|
compatible = "qcom,qsmmu-v500";
|
||
|
|
reg = <0x15000000 0x100000>,
|
||
|
|
<0x15182000 0x20>;
|
||
|
|
reg-names = "base", "tcu-base";
|
||
|
|
#iommu-cells = <2>;
|
||
|
|
qcom,skip-init;
|
||
|
|
qcom,use-3-lvl-tables;
|
||
|
|
qcom,disable-atos;
|
||
|
|
#global-interrupts = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
ranges;
|
||
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,msm-bus,name = "apps_smmu";
|
||
|
|
qcom,msm-bus,num-cases = <2>;
|
||
|
|
qcom,msm-bus,active-only;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<MSM_BUS_MASTER_GEM_NOC_SNOC>,
|
||
|
|
<MSM_BUS_SLAVE_IMEM_CFG>,
|
||
|
|
<0 0>,
|
||
|
|
<MSM_BUS_MASTER_GEM_NOC_SNOC>,
|
||
|
|
<MSM_BUS_SLAVE_IMEM_CFG>,
|
||
|
|
<0 1000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#include "sdmshrike-regulators.dtsi"
|
||
|
|
#include "sdmshrike-pinctrl.dtsi"
|
||
|
|
#include "sdmshrike-bus.dtsi"
|