596 lines
30 KiB
C
596 lines
30 KiB
C
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_PHY_QCOM_SDXPRAIRIE_QMP_USB_H
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#define _DT_BINDINGS_PHY_QCOM_SDXPRAIRIE_QMP_USB_H
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#define USB3_UNI_QSERDES_COM_ATB_SEL1 0x0000
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#define USB3_UNI_QSERDES_COM_ATB_SEL2 0x0004
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#define USB3_UNI_QSERDES_COM_FREQ_UPDATE 0x0008
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#define USB3_UNI_QSERDES_COM_BG_TIMER 0x000C
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#define USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x0010
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#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER1 0x0014
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#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER2 0x0018
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#define USB3_UNI_QSERDES_COM_SSC_PER1 0x001C
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#define USB3_UNI_QSERDES_COM_SSC_PER2 0x0020
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x0024
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x0028
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x002C
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x0030
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x0034
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#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x0038
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#define USB3_UNI_QSERDES_COM_POST_DIV 0x003C
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#define USB3_UNI_QSERDES_COM_POST_DIV_MUX 0x0040
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#define USB3_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0044
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#define USB3_UNI_QSERDES_COM_CLK_ENABLE1 0x0048
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#define USB3_UNI_QSERDES_COM_SYS_CLK_CTRL 0x004C
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#define USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0050
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#define USB3_UNI_QSERDES_COM_PLL_EN 0x0054
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#define USB3_UNI_QSERDES_COM_PLL_IVCO 0x0058
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#define USB3_UNI_QSERDES_COM_CMN_IETRIM 0x005C
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#define USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x0060
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#define USB3_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x0064
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#define USB3_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0068
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#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 0x006C
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#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 0x0070
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#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x0074
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#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x0078
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#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x007C
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#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x0080
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#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x0084
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#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x0088
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#define USB3_UNI_QSERDES_COM_PLL_CNTRL 0x008C
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#define USB3_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0090
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#define USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x0094
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#define USB3_UNI_QSERDES_COM_CML_SYSCLK_SEL 0x0098
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#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL 0x009C
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#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL2 0x00A0
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#define USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x00A4
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#define USB3_UNI_QSERDES_COM_LOCK_CMP_CFG 0x00A8
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#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x00AC
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#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x00B0
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#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x00B4
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#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x00B8
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#define USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x00BC
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#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE0 0x00C0
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#define USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x00C4
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#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE1 0x00C8
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0x00CC
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0x00D0
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x00D4
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0x00D8
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00DC
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#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x00E0
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_INITVAL 0x00E4
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_EN 0x00E8
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00EC
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00F0
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00F4
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00F8
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x00FC
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x0100
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#define USB3_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0104
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_CTRL 0x0108
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x010C
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#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x0110
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#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE0 0x0114
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#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x0118
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#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x011C
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 0x0120
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 0x0124
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 0x0128
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 0x012C
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 0x0130
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0134
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER1 0x0138
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#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER2 0x013C
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#define USB3_UNI_QSERDES_COM_CMN_STATUS 0x0140
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#define USB3_UNI_QSERDES_COM_RESET_SM_STATUS 0x0144
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#define USB3_UNI_QSERDES_COM_RESTRIM_CODE_STATUS 0x0148
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#define USB3_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS 0x014C
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#define USB3_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0150
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#define USB3_UNI_QSERDES_COM_CLK_SELECT 0x0154
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#define USB3_UNI_QSERDES_COM_HSCLK_SEL 0x0158
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#define USB3_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x015C
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#define USB3_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0160
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#define USB3_UNI_QSERDES_COM_PLL_ANALOG 0x0164
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#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE0 0x0168
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#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x016C
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#define USB3_UNI_QSERDES_COM_SW_RESET 0x0170
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#define USB3_UNI_QSERDES_COM_CORE_CLK_EN 0x0174
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#define USB3_UNI_QSERDES_COM_C_READY_STATUS 0x0178
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#define USB3_UNI_QSERDES_COM_CMN_CONFIG 0x017C
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#define USB3_UNI_QSERDES_COM_CMN_RATE_OVERRIDE 0x0180
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#define USB3_UNI_QSERDES_COM_SVS_MODE_CLK_SEL 0x0184
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#define USB3_UNI_QSERDES_COM_DEBUG_BUS0 0x0188
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#define USB3_UNI_QSERDES_COM_DEBUG_BUS1 0x018C
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#define USB3_UNI_QSERDES_COM_DEBUG_BUS2 0x0190
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#define USB3_UNI_QSERDES_COM_DEBUG_BUS3 0x0194
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#define USB3_UNI_QSERDES_COM_DEBUG_BUS_SEL 0x0198
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#define USB3_UNI_QSERDES_COM_CMN_MISC1 0x019C
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#define USB3_UNI_QSERDES_COM_CMN_MISC2 0x01A0
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#define USB3_UNI_QSERDES_COM_CMN_MODE 0x01A4
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#define USB3_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x01A8
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#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x01AC
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#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x01B0
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#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x01B4
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#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x01B8
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#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x01BC
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#define USB3_UNI_QSERDES_TX_BIST_MODE_LANENO 0x0200
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#define USB3_UNI_QSERDES_TX_BIST_INVERT 0x0204
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#define USB3_UNI_QSERDES_TX_CLKBUF_ENABLE 0x0208
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#define USB3_UNI_QSERDES_TX_TX_EMP_POST1_LVL 0x020C
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#define USB3_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x0210
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#define USB3_UNI_QSERDES_TX_TX_DRV_LVL 0x0214
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#define USB3_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET 0x0218
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#define USB3_UNI_QSERDES_TX_RESET_TSYNC_EN 0x021C
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#define USB3_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x0220
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#define USB3_UNI_QSERDES_TX_TX_BAND 0x0224
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#define USB3_UNI_QSERDES_TX_SLEW_CNTL 0x0228
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#define USB3_UNI_QSERDES_TX_INTERFACE_SELECT 0x022C
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#define USB3_UNI_QSERDES_TX_LPB_EN 0x0230
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#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x0234
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#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x0238
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#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x023C
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#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0240
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#define USB3_UNI_QSERDES_TX_PERL_LENGTH1 0x0244
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#define USB3_UNI_QSERDES_TX_PERL_LENGTH2 0x0248
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#define USB3_UNI_QSERDES_TX_SERDES_BYP_EN_OUT 0x024C
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#define USB3_UNI_QSERDES_TX_DEBUG_BUS_SEL 0x0250
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#define USB3_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN 0x0254
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#define USB3_UNI_QSERDES_TX_HIGHZ_DRVR_EN 0x0258
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#define USB3_UNI_QSERDES_TX_TX_POL_INV 0x025C
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#define USB3_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x0260
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN1 0x0264
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN2 0x0268
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN3 0x026C
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN4 0x0270
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN5 0x0274
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN6 0x0278
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN7 0x027C
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#define USB3_UNI_QSERDES_TX_BIST_PATTERN8 0x0280
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#define USB3_UNI_QSERDES_TX_LANE_MODE_1 0x0284
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#define USB3_UNI_QSERDES_TX_LANE_MODE_2 0x0288
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#define USB3_UNI_QSERDES_TX_LANE_MODE_3 0x028C
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#define USB3_UNI_QSERDES_TX_ATB_SEL1 0x0290
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#define USB3_UNI_QSERDES_TX_ATB_SEL2 0x0294
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#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL 0x0298
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#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x029C
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#define USB3_UNI_QSERDES_TX_PRBS_SEED1 0x02A0
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#define USB3_UNI_QSERDES_TX_PRBS_SEED2 0x02A4
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#define USB3_UNI_QSERDES_TX_PRBS_SEED3 0x02A8
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#define USB3_UNI_QSERDES_TX_PRBS_SEED4 0x02AC
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#define USB3_UNI_QSERDES_TX_RESET_GEN 0x02B0
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#define USB3_UNI_QSERDES_TX_RESET_GEN_MUXES 0x02B4
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#define USB3_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN 0x02B8
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#define USB3_UNI_QSERDES_TX_TX_INTERFACE_MODE 0x02BC
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#define USB3_UNI_QSERDES_TX_PWM_CTRL 0x02C0
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#define USB3_UNI_QSERDES_TX_PWM_ENCODED_OR_DATA 0x02C4
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x02C8
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x02CC
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x02D0
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x02D4
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x02D8
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x02DC
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x02E0
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#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x02E4
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#define USB3_UNI_QSERDES_TX_VMODE_CTRL1 0x02E8
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#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 0x02EC
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#define USB3_UNI_QSERDES_TX_BIST_STATUS 0x02F0
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#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT1 0x02F4
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#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT2 0x02F8
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#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 0x02FC
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#define USB3_UNI_QSERDES_TX_LANE_DIG_CONFIG 0x0300
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#define USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x0304
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#define USB3_UNI_QSERDES_TX_PRE_EMPH 0x0308
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#define USB3_UNI_QSERDES_TX_SW_RESET 0x030C
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#define USB3_UNI_QSERDES_TX_DCC_OFFSET 0x0310
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#define USB3_UNI_QSERDES_TX_DIG_BKUP_CTRL 0x0314
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#define USB3_UNI_QSERDES_TX_DEBUG_BUS0 0x0318
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#define USB3_UNI_QSERDES_TX_DEBUG_BUS1 0x031C
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#define USB3_UNI_QSERDES_TX_DEBUG_BUS2 0x0320
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#define USB3_UNI_QSERDES_TX_DEBUG_BUS3 0x0324
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#define USB3_UNI_QSERDES_TX_READ_EQCODE 0x0328
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#define USB3_UNI_QSERDES_TX_READ_OFFSETCODE 0x032C
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#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW 0x0330
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#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH 0x0334
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#define USB3_UNI_QSERDES_TX_VGA_READ_CODE 0x0338
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#define USB3_UNI_QSERDES_TX_VTH_READ_CODE 0x033C
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#define USB3_UNI_QSERDES_TX_DFE_TAP1_READ_CODE 0x0340
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#define USB3_UNI_QSERDES_TX_DFE_TAP2_READ_CODE 0x0344
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#define USB3_UNI_QSERDES_TX_IDAC_STATUS_I 0x0348
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|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_IBAR 0x034C
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_Q 0x0350
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_QBAR 0x0354
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_A 0x0358
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_ABAR 0x035C
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SM_ON 0x0360
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE 0x0364
|
||
|
|
#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR 0x0368
|
||
|
|
#define USB3_UNI_QSERDES_TX_DCC_CAL_STATUS 0x036C
|
||
|
|
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF 0x0400
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x0404
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0408
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF 0x040C
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x0410
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x0414
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x0418
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x041C
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN 0x0420
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x0424
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x0428
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN 0x042C
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x0430
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x0434
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x0438
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x043C
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0440
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x0444
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_PI_CTRL2 0x0448
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x044C
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x0450
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x0454
|
||
|
|
#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x0458
|
||
|
|
#define USB3_UNI_QSERDES_RX_AUX_CONTROL 0x045C
|
||
|
|
#define USB3_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0x0460
|
||
|
|
#define USB3_UNI_QSERDES_RX_RCLK_AUXDATA_SEL 0x0464
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_ENABLE 0x0468
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_INITP 0x046C
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_INITN 0x0470
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_LVL 0x0474
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_MODE 0x0478
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_RESET 0x047C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_TERM_BW 0x0480
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_RCVR_IQ_EN 0x0484
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x0488
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x048C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0490
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0494
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0498
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x049C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_EN 0x04A0
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_ENABLES 0x04A4
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_SIGN 0x04A8
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE 0x04AC
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x04B0
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_1 0x04B4
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_2 0x04B8
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_3 0x04BC
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_4 0x04C0
|
||
|
|
#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 0x04C4
|
||
|
|
#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 0x04C8
|
||
|
|
#define USB3_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH 0x04CC
|
||
|
|
#define USB3_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH 0x04D0
|
||
|
|
#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x04D4
|
||
|
|
#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x04D8
|
||
|
|
#define USB3_UNI_QSERDES_RX_GM_CAL 0x04DC
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB 0x04E0
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB 0x04E4
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x04E8
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x04EC
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x04F0
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x04F4
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x04F8
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x04FC
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME 0x0500
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR 0x0504
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB 0x0508
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB 0x050C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0510
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0514
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x0518
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x051C
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGDET_LVL 0x0520
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0524
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_BAND 0x0528
|
||
|
|
#define USB3_UNI_QSERDES_RX_CDR_FREEZE_UP_DN 0x052C
|
||
|
|
#define USB3_UNI_QSERDES_RX_CDR_RESET_OVERRIDE 0x0530
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_INTERFACE_MODE 0x0534
|
||
|
|
#define USB3_UNI_QSERDES_RX_JITTER_GEN_MODE 0x0538
|
||
|
|
#define USB3_UNI_QSERDES_RX_SJ_AMP1 0x053C
|
||
|
|
#define USB3_UNI_QSERDES_RX_SJ_AMP2 0x0540
|
||
|
|
#define USB3_UNI_QSERDES_RX_SJ_PER1 0x0544
|
||
|
|
#define USB3_UNI_QSERDES_RX_SJ_PER2 0x0548
|
||
|
|
#define USB3_UNI_QSERDES_RX_PPM_OFFSET1 0x054C
|
||
|
|
#define USB3_UNI_QSERDES_RX_PPM_OFFSET2 0x0550
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 0x0554
|
||
|
|
#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 0x0558
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x055C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0560
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0564
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x0568
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x056C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x0570
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x0574
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x0578
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x057C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x0580
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x0584
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x0588
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x058C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0590
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0x0594
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_10_LOW 0x0598
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH 0x059C
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH2 0x05A0
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH3 0x05A4
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH4 0x05A8
|
||
|
|
#define USB3_UNI_QSERDES_RX_PHPRE_CTRL 0x05AC
|
||
|
|
#define USB3_UNI_QSERDES_RX_PHPRE_INITVAL 0x05B0
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x05B4
|
||
|
|
#define USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x05B8
|
||
|
|
#define USB3_UNI_QSERDES_RX_DCC_CTRL1 0x05BC
|
||
|
|
#define USB3_UNI_QSERDES_RX_DCC_CTRL2 0x05C0
|
||
|
|
#define USB3_UNI_QSERDES_RX_VTH_CODE 0x05C4
|
||
|
|
#define USB3_UNI_QSERDES_RX_VTH_MIN_THRESH 0x05C8
|
||
|
|
#define USB3_UNI_QSERDES_RX_VTH_MAX_THRESH 0x05CC
|
||
|
|
#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 0x05D0
|
||
|
|
#define USB3_UNI_QSERDES_RX_PI_CTRL1 0x05D4
|
||
|
|
#define USB3_UNI_QSERDES_RX_PI_CTRL2 0x05D8
|
||
|
|
#define USB3_UNI_QSERDES_RX_PI_QUAD 0x05DC
|
||
|
|
#define USB3_UNI_QSERDES_RX_IDATA1 0x05E0
|
||
|
|
#define USB3_UNI_QSERDES_RX_IDATA2 0x05E4
|
||
|
|
#define USB3_UNI_QSERDES_RX_AUX_DATA1 0x05E8
|
||
|
|
#define USB3_UNI_QSERDES_RX_AUX_DATA2 0x05EC
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTP 0x05F0
|
||
|
|
#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTN 0x05F4
|
||
|
|
#define USB3_UNI_QSERDES_RX_RX_SIGDET 0x05F8
|
||
|
|
#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 0x05FC
|
||
|
|
|
||
|
|
#define USB3_UNI_PCS_LN_PCS_STATUS1 0x0600
|
||
|
|
#define USB3_UNI_PCS_LN_PCS_STATUS2 0x0604
|
||
|
|
#define USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR 0x0608
|
||
|
|
#define USB3_UNI_PCS_LN_PCS_STATUS3 0x060C
|
||
|
|
#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x0610
|
||
|
|
#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x0614
|
||
|
|
#define USB3_UNI_PCS_LN_BIST_CHK_STATUS 0x0618
|
||
|
|
#define USB3_UNI_PCS_LN_INSIG_SW_CTRL1 0x061C
|
||
|
|
#define USB3_UNI_PCS_LN_INSIG_MX_CTRL1 0x0620
|
||
|
|
#define USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 0x0624
|
||
|
|
#define USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 0x0628
|
||
|
|
#define USB3_UNI_PCS_LN_TEST_CONTROL 0x062C
|
||
|
|
#define USB3_UNI_PCS_LN_BIST_CTRL 0x0630
|
||
|
|
#define USB3_UNI_PCS_LN_PRBS_SEED0 0x0634
|
||
|
|
#define USB3_UNI_PCS_LN_PRBS_SEED1 0x0638
|
||
|
|
#define USB3_UNI_PCS_LN_FIXED_PAT_CTRL 0x063C
|
||
|
|
#define USB3_UNI_PCS_LN_EQ_CONFIG 0x0640
|
||
|
|
|
||
|
|
#define USB3_UNI_PCS_LN_PRESET_OVERRIDE_PRE_POST 0x0700
|
||
|
|
#define USB3_UNI_PCS_LN_PRESET_OVERRIDE_PRE_POST_RS 0x0704
|
||
|
|
#define USB3_UNI_PCS_LN_PRESET_OVERRIDE_EN 0x0708
|
||
|
|
#define USB3_UNI_PCS_LN_PRESET_DSBL_L 0x070C
|
||
|
|
#define USB3_UNI_PCS_LN_PRESET_DSBL_H 0x0710
|
||
|
|
#define USB3_UNI_PCS_LN_LANE_OFF_CONFIG 0x0714
|
||
|
|
#define USB3_UNI_PCS_LN_RXEQ_DONE_CONFIG1 0x0718
|
||
|
|
#define USB3_UNI_PCS_LN_RXEQ_DONE_CONFIG2 0x071C
|
||
|
|
#define USB3_UNI_PCS_LN_PCIE_PCS_STATUS 0x0720
|
||
|
|
#define USB3_UNI_PCS_LN_INSIG_SW_CTRL2 0x0724
|
||
|
|
#define USB3_UNI_PCS_LN_INSIG_MX_CTRL2 0x0728
|
||
|
|
|
||
|
|
#define USB3_UNI_PCS_SW_RESET 0x0800
|
||
|
|
#define USB3_UNI_PCS_REVISION_ID0 0x0804
|
||
|
|
#define USB3_UNI_PCS_REVISION_ID1 0x0808
|
||
|
|
#define USB3_UNI_PCS_REVISION_ID2 0x080C
|
||
|
|
#define USB3_UNI_PCS_REVISION_ID3 0x0810
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS1 0x0814
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS2 0x0818
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS3 0x081C
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS4 0x0820
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS5 0x0824
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS6 0x0828
|
||
|
|
#define USB3_UNI_PCS_PCS_STATUS7 0x082C
|
||
|
|
#define USB3_UNI_PCS_DEBUG_BUS_0_STATUS 0x0830
|
||
|
|
#define USB3_UNI_PCS_DEBUG_BUS_1_STATUS 0x0834
|
||
|
|
#define USB3_UNI_PCS_DEBUG_BUS_2_STATUS 0x0838
|
||
|
|
#define USB3_UNI_PCS_DEBUG_BUS_3_STATUS 0x083C
|
||
|
|
#define USB3_UNI_PCS_POWER_DOWN_CONTROL 0x0840
|
||
|
|
#define USB3_UNI_PCS_START_CONTROL 0x0844
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL1 0x0848
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL2 0x084C
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL3 0x0850
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL4 0x0854
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL5 0x0858
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL6 0x085C
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL7 0x0860
|
||
|
|
#define USB3_UNI_PCS_INSIG_SW_CTRL8 0x0864
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL1 0x0868
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL2 0x086C
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL3 0x0870
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL4 0x0874
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL5 0x0878
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL7 0x087C
|
||
|
|
#define USB3_UNI_PCS_INSIG_MX_CTRL8 0x0880
|
||
|
|
#define USB3_UNI_PCS_OUTSIG_SW_CTRL1 0x0884
|
||
|
|
#define USB3_UNI_PCS_OUTSIG_MX_CTRL1 0x0888
|
||
|
|
#define USB3_UNI_PCS_CLAMP_ENABLE 0x088C
|
||
|
|
#define USB3_UNI_PCS_POWER_STATE_CONFIG1 0x0890
|
||
|
|
#define USB3_UNI_PCS_POWER_STATE_CONFIG2 0x0894
|
||
|
|
#define USB3_UNI_PCS_FLL_CNTRL1 0x0898
|
||
|
|
#define USB3_UNI_PCS_FLL_CNTRL2 0x089C
|
||
|
|
#define USB3_UNI_PCS_FLL_CNT_VAL_L 0x08A0
|
||
|
|
#define USB3_UNI_PCS_FLL_CNT_VAL_H_TOL 0x08A4
|
||
|
|
#define USB3_UNI_PCS_FLL_MAN_CODE 0x08A8
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL1 0x08AC
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL2 0x08B0
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL3 0x08B4
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL4 0x08B8
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL5 0x08BC
|
||
|
|
#define USB3_UNI_PCS_TEST_CONTROL6 0x08C0
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0x08C4
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x08C8
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x08CC
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG4 0x08D0
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG5 0x08D4
|
||
|
|
#define USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x08D8
|
||
|
|
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x08DC
|
||
|
|
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG2 0x08E0
|
||
|
|
#define USB3_UNI_PCS_REFGEN_REQ_CONFIG3 0x08E4
|
||
|
|
#define USB3_UNI_PCS_BIST_CTRL 0x08E8
|
||
|
|
#define USB3_UNI_PCS_PRBS_POLY0 0x08EC
|
||
|
|
#define USB3_UNI_PCS_PRBS_POLY1 0x08F0
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT0 0x08F4
|
||
|
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#define USB3_UNI_PCS_FIXED_PAT1 0x08F8
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT2 0x08FC
|
||
|
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#define USB3_UNI_PCS_FIXED_PAT3 0x0900
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT4 0x0904
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT5 0x0908
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT6 0x090C
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT7 0x0910
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT8 0x0914
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT9 0x0918
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT10 0x091C
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT11 0x0920
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT12 0x0924
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT13 0x0928
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT14 0x092C
|
||
|
|
#define USB3_UNI_PCS_FIXED_PAT15 0x0930
|
||
|
|
#define USB3_UNI_PCS_TXMGN_CONFIG 0x0934
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V0 0x0938
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V1 0x093C
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V2 0x0940
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V3 0x0944
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V4 0x0948
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V0_RS 0x094C
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V1_RS 0x0950
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V2_RS 0x0954
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V3_RS 0x0958
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXMGN_V4_RS 0x095C
|
||
|
|
#define USB3_UNI_PCS_G3S2_TXMGN_MAIN 0x0960
|
||
|
|
#define USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS 0x0964
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB 0x0968
|
||
|
|
#define USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB 0x096C
|
||
|
|
#define USB3_UNI_PCS_G3S2_PRE_GAIN 0x0970
|
||
|
|
#define USB3_UNI_PCS_G3S2_POST_GAIN 0x0974
|
||
|
|
#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET 0x0978
|
||
|
|
#define USB3_UNI_PCS_G3S2_PRE_GAIN_RS 0x097C
|
||
|
|
#define USB3_UNI_PCS_G3S2_POST_GAIN_RS 0x0980
|
||
|
|
#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS 0x0984
|
||
|
|
#define USB3_UNI_PCS_RX_SIGDET_LVL 0x0988
|
||
|
|
#define USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL 0x098C
|
||
|
|
#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0x0990
|
||
|
|
#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x0994
|
||
|
|
#define USB3_UNI_PCS_RATE_SLEW_CNTRL1 0x0998
|
||
|
|
#define USB3_UNI_PCS_RATE_SLEW_CNTRL2 0x099C
|
||
|
|
#define USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x09A0
|
||
|
|
#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x09A4
|
||
|
|
#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x09A8
|
||
|
|
#define USB3_UNI_PCS_TSYNC_RSYNC_TIME 0x09AC
|
||
|
|
#define USB3_UNI_PCS_CDR_RESET_TIME 0x09B0
|
||
|
|
#define USB3_UNI_PCS_TSYNC_DLY_TIME 0x09B4
|
||
|
|
#define USB3_UNI_PCS_ELECIDLE_DLY_SEL 0x09B8
|
||
|
|
#define USB3_UNI_PCS_CMN_ACK_OUT_SEL 0x09BC
|
||
|
|
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x09C0
|
||
|
|
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x09C4
|
||
|
|
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 0x09C8
|
||
|
|
#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 0x09CC
|
||
|
|
#define USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x09D0
|
||
|
|
#define USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL 0x09D4
|
||
|
|
#define USB3_UNI_PCS_RX_DCC_CAL_CONFIG 0x09D8
|
||
|
|
#define USB3_UNI_PCS_EQ_CONFIG1 0x09DC
|
||
|
|
#define USB3_UNI_PCS_EQ_CONFIG2 0x09E0
|
||
|
|
#define USB3_UNI_PCS_EQ_CONFIG3 0x09E4
|
||
|
|
#define USB3_UNI_PCS_EQ_CONFIG4 0x09E8
|
||
|
|
#define USB3_UNI_PCS_EQ_CONFIG5 0x09EC
|
||
|
|
|
||
|
|
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS 0x0C00
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS 0x0C04
|
||
|
|
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 0x0C08
|
||
|
|
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 0x0C0C
|
||
|
|
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 0x0C10
|
||
|
|
#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 0x0C14
|
||
|
|
#define USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG 0x0C18
|
||
|
|
#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x0C1C
|
||
|
|
#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x0C20
|
||
|
|
#define USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x0C24
|
||
|
|
#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x0C28
|
||
|
|
#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x0C2C
|
||
|
|
#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x0C30
|
||
|
|
#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x0C34
|
||
|
|
#define USB3_UNI_PCS_PCIE_SIGDET_CNTRL 0x0C38
|
||
|
|
#define USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x0C3C
|
||
|
|
#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x0C40
|
||
|
|
#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x0C44
|
||
|
|
#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x0C48
|
||
|
|
#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x0C4C
|
||
|
|
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x0C50
|
||
|
|
#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x0C54
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 0x0C58
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 0x0C5C
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 0x0C60
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 0x0C64
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 0x0C68
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 0x0C6C
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 0x0C70
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x0C74
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x0C78
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x0C7C
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x0C80
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x0C84
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x0C88
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x0C8C
|
||
|
|
#define USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS 0x0C90
|
||
|
|
#define USB3_UNI_PCS_PCIE_LOCAL_FS 0x0C94
|
||
|
|
#define USB3_UNI_PCS_PCIE_LOCAL_LF 0x0C98
|
||
|
|
#define USB3_UNI_PCS_PCIE_LOCAL_FS_RS 0x0C9C
|
||
|
|
#define USB3_UNI_PCS_PCIE_EQ_CONFIG1 0x0CA0
|
||
|
|
#define USB3_UNI_PCS_PCIE_EQ_CONFIG2 0x0CA4
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE 0x0CA8
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE 0x0CAC
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE 0x0CB0
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE 0x0CB4
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE 0x0CB8
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P10_PRE 0x0CBC
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS 0x0CC0
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS 0x0CC4
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS 0x0CC8
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST 0x0CCC
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST 0x0CD0
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST 0x0CD4
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST 0x0CD8
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST 0x0CDC
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P10_POST 0x0CE0
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS 0x0CE4
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS 0x0CE8
|
||
|
|
#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS 0x0CEC
|
||
|
|
#define USB3_UNI_PCS_PCIE_RXEQEVAL_TIME 0x0CF0
|
||
|
|
|
||
|
|
#define USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x0E00
|
||
|
|
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x0E04
|
||
|
|
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x0E08
|
||
|
|
#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0E0C
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x0E10
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x0E14
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x0E18
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_TX_ECSTART 0x0E1C
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x0E20
|
||
|
|
#define USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x0E24
|
||
|
|
#define USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x0E28
|
||
|
|
#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x0E2C
|
||
|
|
#define USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x0E30
|
||
|
|
#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x0E34
|
||
|
|
#define USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x0E38
|
||
|
|
#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x0E3C
|
||
|
|
#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x0E40
|
||
|
|
#define USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x0E44
|
||
|
|
#define USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x0E48
|
||
|
|
#define USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x0E4C
|
||
|
|
#define USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x0E50
|
||
|
|
#define USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x0E54
|
||
|
|
#define USB3_UNI_PCS_USB3_TEST_CONTROL 0x0E58
|
||
|
|
#define USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x0E5C
|
||
|
|
|
||
|
|
#endif /* _DT_BINDINGS_PHY_QCOM_SDXPRAIRIE_QMP_USB_H */
|