440 lines
11 KiB
C
440 lines
11 KiB
C
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,videocc-sdmmagpie.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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#include "vdd-level-sdmmagpie.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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#define IRIS_DISBALE_MULTIPIPE 10
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_VIDEO_PLL0_OUT_EVEN,
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P_VIDEO_PLL0_OUT_MAIN,
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P_VIDEO_PLL0_OUT_ODD,
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_PLL0_OUT_MAIN, 1 },
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{ P_VIDEO_PLL0_OUT_EVEN, 2 },
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{ P_VIDEO_PLL0_OUT_ODD, 3 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const video_cc_parent_names_0[] = {
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"bi_tcxo",
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"video_pll0",
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"video_pll0_out_even",
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"video_pll0_out_odd",
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"core_bi_pll_test_se",
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};
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static const struct parent_map video_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const video_cc_parent_names_2[] = {
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"bi_tcxo_ao",
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"core_bi_pll_test_se",
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};
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static struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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{ 125000000, 1000000000, 1 },
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};
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static struct alpha_pll_config video_pll0_config = {
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.l = 0x19,
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.frac = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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.test_ctl_hi_val = 0x40000000,
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};
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static struct clk_alpha_pll video_pll0 = {
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.offset = 0x42c,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "video_pll0",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
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F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static const struct freq_tbl ftbl_video_cc_iris_multipipe_clk_src[] = {
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F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
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};
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static struct clk_rcg2 video_cc_iris_clk_src = {
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.cmd_rcgr = 0x7f0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_iris_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "video_cc_iris_clk_src",
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.parent_names = video_cc_parent_names_0,
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.num_parents = 5,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 240000000,
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[VDD_LOW] = 338000000,
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[VDD_LOW_L1] = 365000000,
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[VDD_NOMINAL] = 444000000,
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[VDD_HIGH] = 533000000},
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},
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};
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static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_xo_clk_src = {
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.cmd_rcgr = 0xa98,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_2,
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.freq_tbl = ftbl_video_cc_xo_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "video_cc_xo_clk_src",
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.parent_names = video_cc_parent_names_2,
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.num_parents = 2,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch video_cc_iris_ahb_clk = {
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.halt_reg = 0x8f4,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x8f4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_iris_ahb_clk",
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.parent_names = (const char *[]){
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"video_cc_iris_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_axi_clk = {
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.halt_reg = 0x9ec,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9ec,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs0_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0_core_clk = {
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.halt_reg = 0x890,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x890,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs0_core_clk",
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.parent_names = (const char *[]){
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"video_cc_iris_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_axi_clk = {
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.halt_reg = 0xa0c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0xa0c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs1_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_core_clk = {
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.halt_reg = 0x8d0,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x8d0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvs1_core_clk",
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.parent_names = (const char *[]){
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"video_cc_iris_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvsc_core_clk = {
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.halt_reg = 0x850,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x850,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvsc_core_clk",
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.parent_names = (const char *[]){
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"video_cc_iris_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
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.halt_reg = 0x9cc,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9cc,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_mvsc_ctl_axi_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_venus_ahb_clk = {
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.halt_reg = 0xa6c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0xa6c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_venus_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_xo_clk = {
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.halt_reg = 0x984,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x984,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "video_cc_xo_clk",
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.parent_names = (const char *[]){
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"video_cc_xo_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *video_cc_sdmmagpie_clocks[] = {
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[VIDEO_PLL0] = &video_pll0.clkr,
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[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
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[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
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[VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr,
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[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
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[VIDEO_CC_MVS1_AXI_CLK] = &video_cc_mvs1_axi_clk.clkr,
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[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
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[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
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[VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr,
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[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
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[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
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[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
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};
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static const struct regmap_config video_cc_sdmmagpie_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xb94,
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.fast_io = true,
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};
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static const struct qcom_cc_desc video_cc_sdmmagpie_desc = {
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.config = &video_cc_sdmmagpie_regmap_config,
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.clks = video_cc_sdmmagpie_clocks,
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.num_clks = ARRAY_SIZE(video_cc_sdmmagpie_clocks),
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};
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static const struct of_device_id video_cc_sdmmagpie_match_table[] = {
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{ .compatible = "qcom,videocc-sdmmagpie" },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, video_cc_sdmmagpie_match_table);
|
||
|
|
|
||
|
|
static int video_multipipe_fixup(struct platform_device *pdev,
|
||
|
|
struct regmap *regmap)
|
||
|
|
{
|
||
|
|
void __iomem *base;
|
||
|
|
struct resource *res;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||
|
|
base = devm_ioremap_resource(dev, res);
|
||
|
|
if (IS_ERR(base))
|
||
|
|
return PTR_ERR(base);
|
||
|
|
|
||
|
|
val = readl_relaxed(base);
|
||
|
|
val = (val >> IRIS_DISBALE_MULTIPIPE) & 0x1;
|
||
|
|
|
||
|
|
if (val) {
|
||
|
|
video_pll0_config.l = 0x14;
|
||
|
|
video_cc_iris_clk_src.freq_tbl =
|
||
|
|
ftbl_video_cc_iris_multipipe_clk_src;
|
||
|
|
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOWER] =
|
||
|
|
200000000;
|
||
|
|
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOW] =
|
||
|
|
200000000;
|
||
|
|
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =
|
||
|
|
200000000;
|
||
|
|
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =
|
||
|
|
200000000;
|
||
|
|
video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_HIGH] =
|
||
|
|
200000000;
|
||
|
|
}
|
||
|
|
|
||
|
|
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int video_cc_sdmmagpie_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct regmap *regmap;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
||
|
|
if (IS_ERR(vdd_cx.regulator[0])) {
|
||
|
|
if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
|
||
|
|
dev_err(&pdev->dev,
|
||
|
|
"Unable to get vdd_cx regulator\n");
|
||
|
|
return PTR_ERR(vdd_cx.regulator[0]);
|
||
|
|
}
|
||
|
|
|
||
|
|
regmap = qcom_cc_map(pdev, &video_cc_sdmmagpie_desc);
|
||
|
|
if (IS_ERR(regmap)) {
|
||
|
|
pr_err("Failed to map the video_cc registers\n");
|
||
|
|
return PTR_ERR(regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = video_multipipe_fixup(pdev, regmap);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = qcom_cc_really_probe(pdev, &video_cc_sdmmagpie_desc, regmap);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Failed to register Video CC clocks\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_info(&pdev->dev, "Registered Video CC clocks\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver video_cc_sdmmagpie_driver = {
|
||
|
|
.probe = video_cc_sdmmagpie_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "video_cc-sdmmagpie",
|
||
|
|
.of_match_table = video_cc_sdmmagpie_match_table,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init video_cc_sdmmagpie_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&video_cc_sdmmagpie_driver);
|
||
|
|
}
|
||
|
|
subsys_initcall(video_cc_sdmmagpie_init);
|
||
|
|
|
||
|
|
static void __exit video_cc_sdmmagpie_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&video_cc_sdmmagpie_driver);
|
||
|
|
}
|
||
|
|
module_exit(video_cc_sdmmagpie_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("QTI VIDEO_CC SDMMAGPIE Driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_ALIAS("platform:video_cc-sdmmagpie");
|