108 lines
2.9 KiB
Plaintext
108 lines
2.9 KiB
Plaintext
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Qualcomm Technologies Inc GPI DMA controller
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QCOM GPI DMA controller provides DMA capabilities for
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peripheral buses such as I2C, UART, and SPI.
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==============
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Node Structure
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==============
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Main node properties:
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- #dma-cells
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Usage: required
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Value type: <u32>
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Definition: Number of parameters client will provide. Must be set to 5.
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1st parameter: channel index, 0 for TX, 1 for RX
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2nd parameter: serial engine index
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3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C
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4th parameter: channel ring length in transfer ring elements
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5th parameter: event processing priority, set to 0 for lowest latency
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- compatible
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Usage: required
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Value type: <string>
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Definition: "qcom,gpi-dma"
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- reg
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Usage: required
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Value type: Array of <u32>
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Definition: register address space location and size
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- reg-name
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Usage: required
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Value type: <string>
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Definition: register space name, must be "gpi-top"
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- interrupts
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Usage: required
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Value type: Array of <u32>
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Definition: Array of tuples which describe interrupt line for each GPII
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instance.
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- qcom,max-num-gpii
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Usage: required
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Value type: <u32>
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Definition: Total number of GPII instances available for this controller.
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- qcom,gpii-mask
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Usage: required
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Value type: <u32>
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Definition: Bitmap of supported GPII instances in hlos.
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- qcom,ev-factor
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Usage: required
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Value type: <u32>
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Definition: Event ring transfer size compare to channel transfer ring. Event
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ring length = ev-factor * transfer ring size
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- iommus
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Usage: required
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Value type: <phandle u32 u32>
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Definition: phandle for apps smmu controller and SID, and mask
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for the controller. For more detail please check binding
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documentation arm,smmu.txt
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- qcom,smmu-cfg
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Usage: required
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Value type: <u32>
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Definition: Determine whether GPI driver require to configure SMMU that
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sits behind GPI controller.
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Bit mask:
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BIT(0) : Attach address mapping to endpoint device
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BIT(1) : Set SMMU attribute S1_BYPASS
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BIT(2) : Set SMMU attribute FAST
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BIT(3) : Set SMMU attribute ATOMIC
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- qcom,iova-range
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Usage: required if SMMU S1 translation is enabled
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Value type: Array of <u64>
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Definition: Pair of values describing iova base and size to allocate.
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Optional property:
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- qcom,gpi-ee-offset
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Usage: optional
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Value type: u64
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Definition: Specifies the gsi ee register offset for the QUP.
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========
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Example:
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========
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gpi_dma0: qcom,gpi-dma@0x800000 {
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#dma-cells = <5>;
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compatible = "qcom,gpi-dma";
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
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<0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
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<0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
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<0 256 0>;
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qcom,max-num-gpii = <13>;
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qcom,gpii-mask = <0xfa>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x0016 0x0>;
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qcom,smmu-cfg = <0x1>
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qcom,iova-range = <0x0 0x100000 0x0 0x100000>;
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status = "ok";
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};
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