80 lines
2.0 KiB
Plaintext
80 lines
2.0 KiB
Plaintext
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Qualcomm Technologies Inc PCIe eDMA controller
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QCOM PCIe eDMA controller provides DMA capabilities for
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peripheral connected and uses PCIe to transfer data.
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==============
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Node Structure
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==============
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Main node properties:
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- compatible
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Usage: required
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Value type: <string>
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Definition: "qcom,pci-edma"
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- #dma-cells
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Usage: required
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Value type: <u32>
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Definition: Number of parameters client will provide. Must be set to 2.
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1st parameter: channel index, 0 for TX, 1 for RX
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2nd parameter: event processing priority, set to 0 for highest priority
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- reg
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Usage: required
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Value type: Array (2-cell) of <u32>
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Definition: First cell is eDMA register base address. Second cell is size of
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eDMA register space.
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- interrupts
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Usage: required
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Value type: Array of <u32>
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Definition: Array of tuples which describe interrupt lines for eDMA.
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- interrupts-names
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Usage: required
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Value type: Array of <u32>
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Definition: Array of names which map to interrupt lines for eDMA.
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- interrupt-parent
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Usage: required
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Value type: <phandle>
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Definition: phandle of the interrupt controller that services interrupts for
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this device
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- qcom,n-tl-init
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Usage: optional
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Value type: <u32>
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Definition: Number of transfer and descriptor arrays to start with. If this
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entry is not presetn, default value is 2.
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- qcom,n-tl-ele
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Usage: optional
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Value type: <u32>
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Definition: Number of elements for each transfer and descriptor array. If this
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entry is not present, default value is 1024.
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- qcom,n-max-ev-ch
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Usage: optional
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Value type: <u32>
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Definition: Total number of virtual (client) eDMA channels available. If this
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entry is not present, default value is 32.
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=======
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Example
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=======
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pci_edma: qcom,pci-edma@40002000 {
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compatible = "qcom,pci-edma";
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#dma-cells = <2>;
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reg = <0x40002000 0x2000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pci-edma-int";
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interrupt-parent = <&intc>;
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qcom,n-max-ev-ch = <32>;
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qcom,n-tl-init = <2>;
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qcom,n-tl-ele = <1024>;
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status = "ok";
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};
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