47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
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ARM CPU memory latency monitor device
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arm-memlat-mon is a device that represents the use of the PMU in ARM cores
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to measure the parameters for latency driven memory access patterns.
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Required properties:
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- compatible: Must be "qcom,arm-memlat-mon" or "qcom,arm-cpu-mon"
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- qcom,cpulist: List of CPU phandles to be monitored in a cluster
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- qcom,target-dev: The DT device that corresponds to this master port
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- qcom,core-dev-table: A mapping table of core frequency to a required bandwidth vote at the
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given core frequency.
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Optional properties:
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- qcom,cachemiss-ev: The cache miss event that this monitor is supposed to measure.
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Defaults to 0x17 if not specified.
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- qcom,inst-ev: The instruction count event that this monitor is supposed to measure.
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Defaults to 0x08 if not specified.
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- qcom,stall-cycle-ev: The stall cycle count that this monitor is supposed to measure.
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Assumes 100% stall if not specified.
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- qcom,ddr-type: Optional property indicates ddr type which can support
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different frequencies for a given target.
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Example:
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qcom,arm-memlat-mon {
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compatible = "qcom,arm-memlat-mon";
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qcom,cpulist = <&CPU0 &CPU1>;
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qcom,target-dev = <&memlat0>;
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qcom,cachemiss-ev = <0x2A>;
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qcom,inst-ev = <0x08>;
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qcom,stall-cycle-ev = <0xE7>;
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ddr3-map {
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qcom,ddr-type = <DDR_TYPE_LPDDR3>;
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qcom,core-dev-table =
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< 300000 1525 >,
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< 499200 3143 >,
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< 1881600 5859 >;
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};
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ddr4-map {
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qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
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qcom,core-dev-table =
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< 300000 1525 >,
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< 499200 3143 >,
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< 1881600 5859 >;
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};
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};
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