96 lines
2.6 KiB
Plaintext
96 lines
2.6 KiB
Plaintext
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Qualcomm Technologies, Inc. SDM CPU clock driver
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---------------------------------------------------
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It is the clock controller driver which provides higher frequency
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clocks and allows CPU frequency scaling on sdm based platforms.
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Required properties:
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- compatible: Shall contain following:
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"qcom,cpu-clock-sdm"
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- clocks: Phandle to the clock device.
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- clock-names: Names of the used clocks. Shall contain following:
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"xo_ao", "gpll0_ao"
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- reg: Shall contain base register offset and size.
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- reg-names: Names of the bases for the above registers. Shall contain following:
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"apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"
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- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
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- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
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- cpu-vdd-supply: The regulator powering the APSS C1 RCG and APSS CCI RCG.
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- qcom,speedX-bin-vY-Z: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
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Format: <freq uV>
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This represents the max frequency possible for each possible
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power configuration for a CPU that's binned as speed bin X,
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speed bin revision Y. Version can be between [0-3]. Z
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is the mux id c1 or cci.
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- #clock-cells: Shall contain 1.
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Example:
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clock_cpu: qcom,clock-cpu@0b011050 {
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compatible = "qcom,cpu-clock-sdm";
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clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
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<&gcc GPLL0_AO_OUT_MAIN>;
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clock-names = "xo_ao", "gpll0_ao" ;
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reg = <0xb011050 0x8>,
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<0xb1d1050 0x8>,
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<0xb016000 0x34>,
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<0x00a412c 0x8>;
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reg-names = "apcs-c1-rcg-base",
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"apcs-cci-rcg-base", "apcs_pll", "efuse";
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cpu-vdd-supply = <&apc_vreg_corner>;
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vdd_dig_ao-supply = <&L12A_AO;
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vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;
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qcom,speed0-bin-v0-c1 =
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< 0 0>,
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< 960000000 1>,
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< 1305600000 1>,
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< 1497600000 2>,
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< 1708800000 3>,
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< 1958400000 5>;
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qcom,speed0-bin-v0-cci =
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< 0 0>,
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< 400000000 1>,
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< 533333333 3>;
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qcom,speed1-bin-v0-c1 =
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< 0 0>,
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< 960000000 1>,
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< 1305600000 1>,
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< 1497600000 2>,
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< 1708800000 3>,
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< 1804800000 5>;
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qcom,speed1-bin-v0-cci =
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< 0 0>,
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< 400000000 1>,
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< 533333333 3>;
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qcom,speed4-bin-v0-c1 =
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< 0 0>,
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< 960000000 1>,
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< 1305600000 1>,
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< 1497600000 2>,
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< 1708800000 3>,
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< 1958400000 5>,
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< 2016000000 6>;
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qcom,speed4-bin-v0-cci =
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< 0 0>,
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< 400000000 1>,
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< 533333333 3>;
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qcom,speed5-bin-v0-c1 =
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< 0 0>,
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< 960000000 1>,
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< 1305600000 1>,
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< 1497600000 2>,
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< 1708800000 3>;
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qcom,speed5-bin-v0-cci =
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< 0 0>,
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< 400000000 1>,
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< 533333333 3>;
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#clock-cells = <1>;
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};
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