34 lines
1.0 KiB
Plaintext
34 lines
1.0 KiB
Plaintext
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Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding
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--------------------------------------------------------------------
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Required properties :
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- compatible : Shall contain one of the following:
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"qcom,dispcc-sm8150",
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"qcom,dispcc-sm8150-v2",
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"qcom,dispcc-sm6150",
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"qcom,dispcc-sdmmagpie",
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"qcom,dispcc-trinket",
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"qcom,dispcc-sdmshrike-v2",
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"qcom,dispcc-sa6155",
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"qcom,atoll-dispcc".
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- reg : Shall contain base register location and length.
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- reg-names: Address name. Must be "cc_base".
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- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf
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of the clocks.
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- clock-names: Shall contain "cfg_ahb_clk"
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- clocks: phandle + clock reference to the GCC AHB clock.
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- #clock-cells : Shall contain 1.
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- #reset-cells : Shall contain 1.
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Example:
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clock_dispcc: qcom,dispcc {
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compatible = "qcom,dispcc-sm8150";
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reg = <0xaf00000 0x20000>;
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reg-names = "cc_base";
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vdd_mm-supply = <&pm8150l_s5_level>;
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clock-names = "cfg_ahb_clk";
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clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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